M30800SAGP#U5 Renesas Electronics America, M30800SAGP#U5 Datasheet - Page 62

• Manufacturer Part Number: M30800SAGP#U5
• Description: IC M32C/80 MCU ROMLESS 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30800SAGP#U5

• Core Processor: M16C/80
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, WDT
• Number Of I /o: 45
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

M
R
R
e
E
3
. v
J
2
Table 7.2 Processor Mode and Port Function
0
Data Bus Width
NOTES:
C
1
PM0 Register
9
P0
P1
P2
P3
P4
P4
P4
P5
P5
P5
P5
P5
PM04 Bits in
Processor
8 /
0 .
B
PM05 to
1. The PM05 and PM04 bits cannot be set to "11
2. These ports become address buses when accessing space using the separate bus.
3. The PM15 and PM14 bits in the PM1 register determines which pin outputs the ALE signal. The PM02 bit in the PM0
4. The PM11 and PM10 bits in the PM1 register determine the CS signal and address bus.
Mode
0
0
0
0
0
4
7
0
4
5
6
7
0
0
0
2
to P0
to P1
to P2
to P3
to P4
to P4
to P5
P5
because the microcomputer starts operation using the separate bus after reset.
When the PM05 and PM04 bits are set to "11
memory space per chip-select using the address bus .
register selects either "WRL,WRH" or "BHE,WR" combination.
G
7
N
1
o r
6
o
0 -
. v
provides an indeterminate output when the PM15 and PM14 bits to "00
7
7
7
7
3
6
3
u
1
p
0
0
, 1
0
Chip Mode
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
I/O port
2
Single-
0
0
5
Page 41
external space with
Access All Other CS Areas using
CS (Chip-select signal) or Address bus (A
Address bus
Data bus
A
CS (Chip-select signal) or Address bus (A
Outputs RD, WRL, WRH and BCLK or outputs RD, BHE, WR and BCLK
8-bit data bus
Address bus
Address bus
0
Data bus
/D
HDLA
Access all
A
A
ALE
Access CS1 or CS2 using
D
I/O port
HOLD
16
RDY
0
8
0
to
to
the Multiplexed Bus
to
to
the Separate Bus
(Refer to 7.2 Bus Control for details)
f o
A
A
(3)
D
A
(2)
Memory Expansion Mode/ Microprocessor Mode
"01
(3)
7
15
7
19
/D
3
3
2
7
", "10
0
Access one or more
external space with
Address bus/
Data bus
A
(Refer to 7.2 Bus Control for details)
Address bus
Data bus
A
16-bit data bus
8
Address bus
0
2
/D
Data bus
/D
A
"
Data bus
HDLA
D
D
ALE
8
16
HOLD
8
0
RDY
0
to
to
to
2
to
to
2
" in memory expansion mode, the microcomputer accesses 64-Kbyte
A
(2)
" (access all CS areas using multiplexed bus) in microprocessor mode
D
A
(Refer to 7.2 Bus Control for details)
D
A
(3)
(2)
15
7
15
19
(3)
7
/D
/D
7
15
external space with
Address bus
Address bus
Address bus
8-bit data bus
A
Data bus
A
Access all
HDLA
A
I/O port
ALE
D
Access all CS Areas using
16
8
HOLD
0
RDY
0
to
to
to
to
A
A
the Separate Bus
A
(3)
D
15
23
7
20
19
(3)
7
(3)
)
to A
"00
Access one or more
22
2
external space with
"
Address bus
16-bit data bus
)
Address bus
Address bus
Data bus
A
Data bus
D
2
(4)
HDLA
D
A
16
ALE
A
" (no ALE). It cannot be used as an I/O port.
8
HOLD
8
0
RDY
0
to
to
to
to
to
D
A
A
D
A
(3)
15
19
15
(3)
7
7
(4)
external space with
Address bus
Data bus
A
Address bus
0
8-bit data bus
Memory Expansion Mode
/D
A
HDLA
Access all
I/O port
I/O port
I/O port
ALE
Access all CS Areas using
8
HOLD
0
RDY
to
to
the Multiplexed Bus
A
A
(3)
15
7
(3)
/D
7
"11
Access one or more
Address bus/
Data bus
A
external space with
2
Address bus
Data bus
A
"
8
16-bit data bus
(1)
/D
0
/D
HDLA
8
ALE
I/O port
I/O port
I/O port
HOLD
0
to
RDY
to
A
A
15
(3)
7
(3)
/D
/D
7. Bus
15
7