D12312SVF20V Renesas Electronics America, D12312SVF20V Datasheet - Page 152
D12312SVF20V
Manufacturer Part Number
D12312SVF20V
Description
IC H8S/2312S MCU ROMLESS 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of D12312SVF20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12312SVF20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 5 Interrupt Controller
Figure 5.3 shows the timing of setting IRQnF.
The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16.
Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for
input or output. Therefore, when a pin is used as an external interrupt input pin, do not clear the
corresponding DDR bit to 0 and use the pin as an I/O pin for another function.
5.3.2
There are 43 sources for internal interrupts from on-chip supporting modules.
• For each on-chip supporting module there are flags that indicate the interrupt request status,
• The interrupt priority level can be set by means of IPR.
• The DTC can be activated by a TPU, SCI, or other interrupt request. When the DTC is
5.3.3
Table 5.4 shows interrupt exception handling sources, vector addresses, and interrupt priorities.
For default priorities, the lower the vector number, the higher the priority. The DTC can also be
activated by some interrupt sources.
Priorities among modules can be set by means of IPR. The situation when two or more modules
are set to the same priority, and priorities within a module, are fixed as shown in table 5.4.
Rev.7.00 Feb. 14, 2007 page 118 of 1108
REJ09B0089-0700
input pin
and enable bits that select enabling or disabling of these interrupts. If both of these are set to 1
for a particular interrupt source, an interrupt request is issued to the interrupt controller.
activated by an interrupt, the interrupt control mode and interrupt mask bits have no effect.
IRQnF
IRQn
φ
Internal Interrupts
Interrupt Exception Vector Table
Figure 5.3 Timing of Setting IRQnF
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