D12312SVF20V Renesas Electronics America, D12312SVF20V Datasheet - Page 35
D12312SVF20V
Manufacturer Part Number
D12312SVF20V
Description
IC H8S/2312S MCU ROMLESS 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of D12312SVF20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12312SVF20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 1 Overview
Section 1 Overview
1.1
Overview
The H8S/2319 Group is a series of microcomputer (MCU: microcomputer unit), built around the
H8S/2000 CPU, employing Renesas's proprietary architecture, and equipped with supporting
functions on-chip.
The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general
registers and a concise, optimized instruction set designed for high-speed operation, and can
address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300
and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300,
H8/300L, or H8/300H Series.
On-chip supporting functions required for system configuration include data transfer controller
(DTC) bus masters, ROM and RAM, a 16-bit timer-pulse unit (TPU), 8-bit timer, watchdog timer
(WDT), serial communication interface (SCI), A/D converter, D/A converter, and I/O ports.
Single-power-supply flash memory (F-ZTAT™ * ) and mask ROM versions are available,
providing a quick and flexible response to conditions from ramp-up through full-scale volume
production, even for applications with frequently changing specifications. ROM is connected to
the CPU via a 16-bit data bus, enabling both byte and word data to be accessed in one state.
Instruction fetching is thus speeded up, and processing speed increased.
The features of the H8S/2319 Group are shown in table 1.1.
Note: * F-ZTAT is a trademark of Renesas Technology Corp.
Rev.7.00 Feb. 14, 2007 page 1 of 1108
REJ09B0089-0700
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