D12312SVF20V Renesas Electronics America, D12312SVF20V Datasheet - Page 801

IC H8S/2312S MCU ROMLESS 100QFP

D12312SVF20V

Manufacturer Part Number
D12312SVF20V
Description
IC H8S/2312S MCU ROMLESS 100QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Datasheets

Specifications of D12312SVF20V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
SCI, SmartCard
Peripherals
POR, PWM, WDT
Number Of I /o
70
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-QFP
For Use With
EDK2329 - DEV EVALUATION KIT H8S/2329
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12312SVF20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
(3) Operating frequency error
Operating frequency is calculated from the received value of the input frequency and the
multiplication or division ratio. The input frequency is input to the LSI and the LSI is operated at
the operating frequency. The expression is given below.
The calculated operating frequency should be checked to ensure that it is within the range of
minimum to maximum frequencies which are available with the clock modes of the specified
device. When it is out of this range, an operating frequency error is generated.
(4) Bit rate
Peripheral operating clock (φ), bit rate (B), clock select (CKS) in the serial mode register (SMR).
The error as calculated by the method below is checked to ensure that it is less than 4%. When it
is 4% or more, a bit-rate selection error is generated.
When the new bit rate is selectable, the rate will be set in the register after sending ACK in
response. The host will send an ACK with the new bit rate for confirmation and the boot program
will response with that rate.
Confirmation
• Confirmation, H'06, (1 byte): Confirmation of a new bit rate
Response
• Response, H'06, (1 byte): Response to confirmation of a new bit rate
The sequence of new bit-rate selection is shown in figure 17.85.
Operating frequency = Input frequency × Multiplication ratio , or
Operating frequency = Input frequency ÷ Division ratio
Error (%) = {[
H'06
H'06
(N+1) * B * 64 * 2
φ * 10
6
(2*n−1)
] − 1} * 100
Rev.7.00 Feb. 14, 2007 page 767 of 1108
REJ09B0089-0700
Section 17 ROM

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