D12312SVF20V Renesas Electronics America, D12312SVF20V Datasheet - Page 482

• Manufacturer Part Number: D12312SVF20V
• Description: IC H8S/2312S MCU ROMLESS 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of D12312SVF20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: SCI, SmartCard
• Peripherals: POR, PWM, WDT
• Number Of I /o: 70
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• For Use With: EDK2329 - DEV EVALUATION KIT H8S/2329
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 12 Serial Communication Interface (SCI)
Bit 2—Transmit End (TEND): Indicates that there is no valid data in TDR when the last bit of
the transmit character is sent, and transmission has been ended.
The TEND flag is read-only and cannot be modified.
Bit 2
TEND
0
1
Bit 1—Multiprocessor Bit (MPB): When reception is performed using multiprocessor format in
asynchronous mode, MPB stores the multiprocessor bit in the receive data.
MPB is a read-only bit, and cannot be modified.
Bit 1
MPB
0
1
Note: * Retains its previous state when the RE bit in SCR is cleared to 0 with multiprocessor
Bit 0—Multiprocessor Bit Transfer (MPBT): When transmission is performed using
multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to
the transmit data.
The MPBT bit setting is invalid when multiprocessor format is not used, when not transmitting,
and in synchronous mode.
Bit 0
MPBT
0
1
Rev.7.00 Feb. 14, 2007 page 448 of 1108
REJ09B0089-0700
format.
Description
[Clearing conditions]
•
•
[Setting conditions]
•
•
Description
[Clearing condition]
When data with a 0 multiprocessor bit is received
[Setting condition]
When data with a 1 multiprocessor bit is received
Description
Data with a 0 multiprocessor bit is transmitted
Data with a 1 multiprocessor bit is transmitted
When 0 is written to TDRE after reading TDRE = 1
When the DTC is activated by a TXI interrupt and writes data to TDR
When the TE bit in SCR is 0
When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character
(Initial value) *
(Initial value)
(Initial value)