HD64F3664BPV Renesas Electronics America, HD64F3664BPV Datasheet - Page 261

• Manufacturer Part Number: HD64F3664BPV
• Description: MCU 3/5V 32K,PB-FREE 42-DIP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3664BPV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 42-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.8.2
When TE is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are
determined by PCR and PDR. This can be used to set the TxD pin to mark state (high level) or
send a break during serial data transmission. To maintain the communication line at mark state
until TE is set to 1, set both PCR and PDR to 1. As TE is cleared to 0 at this point, the TxD pin
becomes an I/O port, and 1 is output from the TxD pin. To send a break during serial transmission,
first set PCR to 1 and PDR to 0, and then clear TE to 0. When TE is cleared to 0, the transmitter is
initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is
output from the TxD pin.
14.8.3
Transmission cannot be started when a receive error flag (OER, PER, or FER) is set to 1, even if
the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting
transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared
to 0.
14.8.4
In asynchronous mode, the SCI3 operates on a basic clock with a frequency of 16 times the
transfer rate. In reception, the SCI3 samples the falling edge of the start bit using the basic clock,
and performs internal synchronization. Receive data is latched internally at the rising edge of the
8th pulse of the basic clock as shown in figure 14.19.
Thus, the reception margin in asynchronous mode is given by formula (1) below.
M = (0.5 –
Where N: Ratio of bit rate to clock (N = 16)
D: Clock duty (D = 0.5 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock rate deviation
Mark State and Break Sending
Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
2N
1
) –
D – 0.5
N
– (L – 0.5) F
100(%)
Section 14 Serial Communication Interface 3 (SCI3)
Rev. 6.00 Mar. 24, 2006 Page 231 of 412
... Formula (1)
REJ09B0142-0600