HD64F3664BPV Renesas Electronics America, HD64F3664BPV Datasheet - Page 86

MCU 3/5V 32K,PB-FREE 42-DIP

HD64F3664BPV

Manufacturer Part Number
HD64F3664BPV
Description
MCU 3/5V 32K,PB-FREE 42-DIP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet

Specifications of HD64F3664BPV

Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
I²C, SCI
Peripherals
PWM, WDT
Number Of I /o
29
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
42-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Section 3 Exception Handling
3.2.4
IRR1 is a status flag register for direct transition interrupts, timer A overflow interrupts, and IRQ3
to IRQ0 interrupt requests.
Rev. 6.00 Mar. 24, 2006 Page 56 of 412
REJ09B0142-0600
Bit
7
6
5
4
3
2
1
Interrupt Flag Register 1 (IRR1)
Bit Name
IRRDT
IRRTA
IRRI3
IRRI2
IRRI1
Initial
Value
0
0
1
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Description
Direct Transfer Interrupt Request Flag
[Setting condition]
When a direct transfer is made by executing a SLEEP
instruction while DTON in SYSCR2 is set to 1.
[Clearing condition]
When IRRDT is cleared by writing 0
Timer A Interrupt Request Flag
[Setting condition]
When the timer A counter value overflows
[Clearing condition]
When IRRTA is cleared by writing 0
Reserved
These bits are always read as 1.
IRQ3 Interrupt Request Flag
[Setting condition]
When IRQ3 pin is designated for interrupt input and
the designated signal edge is detected.
[Clearing condition]
When IRRI3 is cleared by writing 0
IRQ2 Interrupt Request Flag
[Setting condition]
When IRQ2 pin is designated for interrupt input and
the designated signal edge is detected.
[Clearing condition]
When IRRI2 is cleared by writing 0
IRQ1 Interrupt Request Flag
[Setting condition]
When IRQ1 pin is designated for interrupt input and
the designated signal edge is detected.
[Clearing condition]
When IRRI1 is cleared by writing 0

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