HD64F3664BPV Renesas Electronics America, HD64F3664BPV Datasheet - Page 291

MCU 3/5V 32K,PB-FREE 42-DIP

HD64F3664BPV

Manufacturer Part Number
HD64F3664BPV
Description
MCU 3/5V 32K,PB-FREE 42-DIP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet

Specifications of HD64F3664BPV

Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
I²C, SCI
Peripherals
PWM, WDT
Number Of I /o
29
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
42-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
15.4.8
The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched
internally. Figure 15.12 shows a block diagram of the noise canceler circuit.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA)
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
Noise Canceler
SCL or
SDA input
signal
Sampling
clock
Figure 15.12 Block Diagram of Noise Canceler
D
Sampling clock
System clock
period
Latch
C
Q
D
Latch
C
Q
Rev. 6.00 Mar. 24, 2006 Page 261 of 412
detector
Match
Section 15 I
2
C Bus Interface (IIC)
Internal
SCL or
SDA
signal
REJ09B0142-0600

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