DF36034GFPJ Renesas Electronics America, DF36034GFPJ Datasheet
DF36034GFPJ
Specifications of DF36034GFPJ
HD64F36034GFPJ
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DF36034GFPJ Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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H8/36057Group, 16 H8/36037Group Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Series The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be ...
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Rev. 4.00 Mar. 15, 2006 Page ii of xxxii ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test ...
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Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip ...
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The H8/36057 Group and H8/36037 Group are single-chip microcomputers made up of the high- speed H8/300H CPU employing Renesas Technology-original architecture as their cores, and the peripheral functions required to configure a system. The H8/300H CPU has an instruction set ...
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Notes: When using an on-chip emulator (E7, E8) for H8/36057 and H8/36037 program development and debugging, the following restrictions must be noted. 1. The NMI pin is reserved for the E7 or E8, and cannot be used. 2. Pins P85, ...
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Application notes: Document Title H8S, H8/300 Series C/C++ Compiler Package Application Note Single Power Supply F-ZTAT Rev. 4.00 Mar. 15, 2006 Page viii of xxxii TM On-Board Programming Document No. REJ05B0464 REJ05B0520 ...
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Section 1 Overview................................................................................................1 1.1 Features................................................................................................................................. 1 1.2 Internal Block Diagram......................................................................................................... 3 1.3 Pin Arrangement ................................................................................................................... 4 1.4 Pin Functions ........................................................................................................................ 5 Section 2 CPU........................................................................................................9 2.1 Address Space and Memory Map ....................................................................................... 10 2.2 Register Configuration........................................................................................................ 14 2.2.1 General Registers................................................................................................ 15 ...
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Interrupt Enable Register 2 (IENR2) .................................................................. 55 3.2.5 Interrupt Flag Register 1 (IRR1)......................................................................... 55 3.2.6 Interrupt Flag Register 2 (IRR2)......................................................................... 57 3.2.7 Wakeup Interrupt Flag Register (IWPR) ............................................................ 57 3.3 Reset Exception Handling .................................................................................................. 59 3.4 Interrupt Exception Handling ...
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Mode Transitions and States of LSI.................................................................................... 82 6.2.1 Sleep Mode ......................................................................................................... 84 6.2.2 Standby Mode ..................................................................................................... 84 6.2.3 Subsleep Mode.................................................................................................... 85 6.2.4 Subactive Mode .................................................................................................. 85 6.3 Operating Frequency in Active Mode................................................................................. 86 6.4 Direct Transition ................................................................................................................. 86 6.4.1 ...
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Port Pull-Up Control Register 1 (PUCR1)........................................................ 114 9.1.5 Pin Functions .................................................................................................... 114 9.2 Port 2................................................................................................................................. 116 9.2.1 Port Control Register 2 (PCR2) ........................................................................ 117 9.2.2 Port Data Register 2 (PDR2) ............................................................................ 117 9.2.3 Port Mode Register 3 (PMR3) .......................................................................... ...
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Interval Timer Operation .................................................................................. 147 10.4.2 Auto-Reload Timer Operation .......................................................................... 147 10.4.3 Event Counter Operation .................................................................................. 147 10.5 Timer B1 Operating Modes .............................................................................................. 148 Section 11 Timer V............................................................................................149 11.1 Features............................................................................................................................. 149 11.2 Input/Output Pins.............................................................................................................. 151 11.3 Register Descriptions........................................................................................................ 151 ...
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Counter Operation ............................................................................................ 187 12.4.2 Waveform Output by Compare Match.............................................................. 191 12.4.3 Input Capture Function ..................................................................................... 195 12.4.4 Synchronous Operation..................................................................................... 198 12.4.5 PWM Mode ...................................................................................................... 200 12.4.6 Reset Synchronous PWM Mode....................................................................... 206 12.4.7 Complementary PWM Mode............................................................................ 210 12.4.8 Buffer ...
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Clock................................................................................................................. 278 14.5.2 SCI3 Initialization............................................................................................. 278 14.5.3 Serial Data Transmission .................................................................................. 279 14.5.4 Serial Data Reception (Clocked Synchronous Mode)....................................... 281 14.5.5 Simultaneous Serial Data Transmission and Reception.................................... 283 14.6 Multiprocessor Communication Function......................................................................... 285 14.6.1 Multiprocessor Serial Data Transmission ......................................................... ...
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Message Control (MCn0, MCn4 to MCn7 [ 3]) ................................... 319 15.4.2 Local Acceptance Filter Mask (LAFMHn1, LAFMHn0, LAFMLn1, LAFMLn0 [ 3]) ........................ 322 15.4.3 Message Data (MDn0 to MDn7 [ ...
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Interrupt Requests ............................................................................................. 377 16.5 Usage Note........................................................................................................................ 378 Section 17 Subsystem Timer (Subtimer) ...........................................................379 17.1 Features............................................................................................................................. 379 17.2 Register Descriptions........................................................................................................ 381 17.2.1 Subtimer Control Register (SBTCTL) .............................................................. 381 17.2.2 Subtimer Counter (SBTDCNT) ........................................................................ 382 17.2.3 Ring Oscillator Prescaler Setting ...
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Power-On Reset Circuit .................................................................................... 408 19.3.2 Low-Voltage Detection Circuit......................................................................... 409 Section 20 Power Supply Circuit ...................................................................... 413 20.1 When Using Internal Power Supply Step-Down Circuit .................................................. 413 20.2 When Not Using Internal Power Supply Step-Down Circuit ........................................... 414 Section ...
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Appendix B I/O Port Block Diagrams ...............................................................517 B.1 I/O Port Block Diagrams .................................................................................................. 517 B.2 Port States in Each Operating State .................................................................................. 544 Appendix C Product Code Lineup.....................................................................545 Appendix D Package Dimensions .....................................................................547 Main Revisions and Additions in this Edition ...
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Rev. 4.00 Mar. 15, 2006 Page xx of xxxii ...
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Section 1 Overview Figure 1.1 Internal Block Diagram of F-ZTAT Figure 1.2 Pin Arrangement of F-ZTAT Section 2 CPU Figure 2.1 Memory Map (1) ......................................................................................................... 11 Figure 2.1 Memory Map (2) ......................................................................................................... 12 Figure 2.1 Memory Map (3) ......................................................................................................... 13 ...
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Figure 5.5 Typical Connection to Ceramic Resonator.................................................................. 75 Figure 5.6 Example of External Clock Input ................................................................................ 75 Figure 5.7 Example of Incorrect Board Design ............................................................................ 76 Section 6 Power-Down Modes Figure 6.1 Mode Transition Diagram ........................................................................................... 82 Section 7 ROM ...
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Section 12 Timer Z Figure 12.1 Timer Z Block Diagram .......................................................................................... 165 Figure 12.2 Timer Z (Channel 0) Block Diagram ...................................................................... 166 Figure 12.3 Timer Z (Channel 1) Block Diagram ...................................................................... 167 Figure 12.4 Example of Outputs in Reset Synchronous ...
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Figure 12.36 Input Capture Buffer Operation............................................................................. 221 Figure 12.37 Example of Buffer Operation Setting Procedure................................................... 222 Figure 12.38 Example of Buffer Operation (1) (Buffer Operation for Output Compare Register) ................................................. 223 Figure 12.39 Example of Compare Match Timing for Buffer ...
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Figure 14.5 Example of SCI3 Transmission in Asynchronous Mode (8-Bit Data, Parity, One Stop Bit) ........................................................................... 272 Figure 14.6 Sample Serial Transmission Data Flowchart (Asynchronous Mode)...................... 273 Figure 14.7 Example of SCI3 Reception in Asynchronous Mode (8-Bit Data, Parity, One ...
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Figure 15.15 Set Timing for Message Reception ....................................................................... 338 Figure 15.16 RXPR/RFPR Set/Clear Timing when Overrun/Overwrite Occurs........................ 339 Figure 15.17 Flowchart for Changing ID, MBCR, and LAFM of Receive Mailbox.................. 341 Figure 15.18 Flowchart for Transition between Active Mode and ...
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Figure 19.4 Operational Timing of LVDI Circuit....................................................................... 411 Figure 19.5 Timing for Operation/Release of Low-Voltage Detection Circuit .......................... 412 Section 20 Power Supply Circuit Figure 20.1 Power Supply Connection when Internal Step-Down Circuit is Used .................... 413 Figure 20.2 Power ...
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Figure B.17 Port 7 Block Diagram (P71) ................................................................................... 533 Figure B.18 Port 7 Block Diagram (P70) ................................................................................... 534 Figure B.19 Port 8 Block Diagram (P87 to P85) ........................................................................ 535 Figure B.20 Port 9 Block Diagram (P97) ................................................................................... 536 Figure B.21 ...
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Section 1 Overview Table 1.1 Pin Functions ............................................................................................................ 5 Section 2 CPU Table 2.1 Operation Notation ................................................................................................. 21 Table 2.2 Data Transfer Instructions....................................................................................... 22 Table 2.3 Arithmetic Operations Instructions (1) ................................................................... 23 Table 2.3 Arithmetic Operations Instructions (2) ................................................................... 24 ...
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Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible................................................................................................................... 98 Table 7.4 Reprogram Data Computation Table .................................................................... 102 Table 7.5 Additional-Program Data Computation Table ...................................................... 102 Table 7.6 Programming Time ............................................................................................... 102 Table 7.7 ...
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Table 15.4 Interrupt Requests ................................................................................................. 344 Table 15.5 Test Mode Settings ............................................................................................... 345 Section 16 Synchronous Serial Communication Unit (SSU) Table 16.1 Pin Configuration.................................................................................................. 349 Table 16.2 Relationship between Communication Modes and Input/Output Pins.................. 362 Table 16.3 Interrupt Requests ................................................................................................. ...
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Appendix A Instruction Set Table A.1 Instruction Set....................................................................................................... 489 Table A.2 Operation Code Map (1) ....................................................................................... 502 Table A.2 Operation Code Map (2) ....................................................................................... 503 Table A.2 Operation Code Map (3) ....................................................................................... 504 Table A.3 Number of States Required for ...
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Features High-speed H8/300H central processing unit with an internal 16-bit architecture Upward-compatible with H8/300 CPU on an object level Sixteen 16-bit general registers 62 basic instructions Various peripheral functions Timer B1 (8-bit timer) Timer V (8-bit timer) Timer Z ...
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Section 1 Overview On-chip memory Product Classification Flash memory version H8/36057F TM (F-ZTAT version) H8/36054F H8/36037F H8/36034F Masked ROM version H8/36057 H8/36054 H8/36037 H8/36036 H8/36035 H8/36034 H8/36033 H8/36032 General I/O ports I/O pins: 45 I/O pins, including 8 large current ...
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Internal Block Diagram Internal oscillator P10 P11 P12 P14/IRQ0 P15/IRQ1/TMIB1 P16/IRQ2 P17/IRQ3/TRGV P20/SCK3 P21/RXD P22/TXD P23 P24 P90/SCS P91/SSCK P92/SSO P93/SSI P94 P95 P96/HRxD P97/HTxD P57 P56 P55/WKP5/ADTRG P54/WKP4 P53/WKP3 P52/WKP2 P51/WKP1 P50/WKP0 Notes: 1. The SCI3_2 is incorporated ...
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Section 1 Overview 1.3 Pin Arrangement P71/RXD_2 P72/TXD_2 P14/IRQ0 52 P15/IRQ1/TMIB1 P16/IRQ2 53 54 P17/IRQ3/TRGV 55 P93/SSI ...
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Pin Functions Table 1.1 Pin Functions Pin No. FP-64K Type Symbol FP-64A Power source pins Clock pins OSC1 11 OSC2 10 RES System 7 control TEST 8 ...
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Section 1 Overview Pin No. FP-64K Type Symbol FP-64A Timer Z FTIOA0 36 FTIOB0 34 FTIOC0 33 FTIOD0 32 FTIOA1 37 FTIOB1 FTIOD1 Serial com- TXD, 46, 50 munication TXD_2* interface RXD, 45, 49 (SCI) RXD_2* ...
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Pin No. FP-64K Type Symbol FP-64A I/O ports PB7 to PB0 P17 to P14 54, P12 to P10 P24 to P20 31 I/O P57 to P50 13, ...
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Section 1 Overview Rev. 4.00 Mar. 15, 2006 Page 8 of 556 REJ09B0026-0400 ...
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This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward-compatible with the H8/300CPU, and supports only normal mode, which has a 64-kbyte address space. Upward-compatible with H8/300 CPUs Can execute H8/300 CPUs object programs Additional eight ...
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Section 2 CPU Power-down state Transition to power-down state by SLEEP instruction 2.1 Address Space and Memory Map The address space of this LSI is 64 kbytes, which includes the program area and the data area. Figures 2.1 show the ...
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HD64F36057 HD64F36057G HD64F36037 HD64F36037G (Flash memory version) H'0000 Interrupt vector H'0049 H'004A On-chip ROM (56 kbytes) H'DFFF Not used H'EC00 On-chip RAM (1 kbyte) H'EFFF Not used H'F600 Internal I/O register H'F77F H'F780 (1-kbyte work area for flash memory programming) ...
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Section 2 CPU HD64336057G HD64336057 (Masked ROM version) H'0000 H'0000 Interrupt vector H'0049 H'0049 H'004A H'004A H'7FFF On-chip ROM (56 kbytes) H'DFFF Not used H'EC00 H'EC00 On-chip RAM (1 kbyte) H'EFFF H'EFFF Not used H'F600 H'F600 Internal I/O register H'F77F ...
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HD64336035G HD64336035 (Masked ROM version) (Masked ROM version) H'0000 H'0000 Interrupt vector H'0049 H'0049 H'004A H'004A On-chip ROM (40 kbytes) H'7FFF H'9FFF Not used H'EC00 H'EC00 On-chip RAM (1 kbyte) H'EFFF H'EFFF Not used H'F600 H'F600 Internal I/O register H'F77F ...
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Section 2 CPU 2.2 Register Configuration The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), and an 8-bit ...
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General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a data register, it ...
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Section 2 CPU SP (ER7) Figure 2.4 Relationship between Stack Pointer and Stack Area 2.2.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 ...
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Initial Bit Bit Name Value Undefined R Undefined R Undefined R Undefined R Undefined R Undefined R Undefined R/W R/W Description R/W Interrupt ...
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Section 2 CPU 2.3 Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … ...
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Data Type General Data Format Register Word data Rn Word data En 15 MSB Longword ERn data 31 MSB [Legend] ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL ...
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Section 2 CPU 2.3.2 Memory Data Formats Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and longword data in memory, however word or longword data must begin at an even address ...
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Instruction Set 2.4.1 Table of Instructions Classified by Function The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each functional category. The notation used in tables 2.2 to 2.9 is defined below. Table 2.1 ...
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Section 2 CPU Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers ( E7), and 32-bit registers/address register (ER0 to ER7). Table 2.2 Data Transfer Instructions Instruction Size* Function MOV ...
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Table 2.3 Arithmetic Operations Instructions (1) Instruction Size* Function ADD B/W/L Rd ± Rs SUB Performs addition or subtraction on data in two general registers immediate data and data in a general register (immediate byte data cannot be ...
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Section 2 CPU Table 2.3 Arithmetic Operations Instructions (2) Instruction Size* Function DIVXS B/W Rd ÷ Rs Performs signed division on data in two general registers: either 16 bits ÷ 8 bits quotient and 16-bit remainder. CMP B/W/L Rd – ...
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Table 2.4 Logic Operations Instructions Instruction Size* Function AND B/W/L Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd Performs a logical OR operation on a general register and ...
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Section 2 CPU Table 2.6 Bit Manipulation Instructions (1) Instruction Size* Function BSET B 1 Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower ...
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Table 2.6 Bit Manipulation Instructions (2) Instruction Size* Function BXOR B C XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C XORs the ...
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Section 2 CPU Table 2.7 Branch Instructions Instruction Size Function Bcc* — Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS BCC(BHS) BCS(BLO) BNE BEQ BVC BVS ...
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Table 2.8 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling. RTE — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. LDC B/W (EAs) Moves the source operand contents to the ...
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Section 2 CPU Table 2.9 Block Data Transfer Instructions Instruction Size Function EEPMOV.B — if R4L else next; EEPMOV.W — else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number ...
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Basic Instruction Formats H8/300H CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc). Figure 2.7 shows examples of instruction ...
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Section 2 CPU 2.5 Addressing Modes and Effective Address Calculation The following describes the H8/300H CPU. In this LSI, the upper eight bits are ignored in the generated 24-bit address, so the effective address is 16 bits. 2.5.1 Addressing Modes ...
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Register Indirect—@ERn The register field of the instruction code specifies an address register (ERn), the lower 24 bits of which contain the address of the operand on memory. (3) Register Indirect with Displacement—@(d:16, ERn) or @(d:24, ERn) A 16-bit ...
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Section 2 CPU Table 2.11 Absolute Address Access Ranges Absolute Address 8 bits (@aa:8) 16 bits (@aa:16) 24 bits (@aa:24) (6) Immediate—#xx:8, #xx:16, or #xx:32 The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. ...
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Specified by @aa:8 Figure 2.8 Branch Address Specification in Memory Indirect Mode Dummy Branch address Rev. 4.00 Mar. 15, 2006 Page 35 of 556 Section 2 CPU REJ09B0026-0400 ...
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Section 2 CPU 2.5.2 Effective Address Calculation Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI, the upper 8 bits of the effective address are ignored in order to generate a 16-bit effective address. ...
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Table 2.12 Effective Address Calculation (2) Addressing Mode and Instruction Format Absolute address Immediate [Legend] r, rm,rn : Register field op : Operation field disp : Displacement IMM : Immediate data abs : Absolute address Effective Address Calculation PC contents ...
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Section 2 CPU 2.6 Basic Bus Cycle CPU operation is synchronized by a system clock ( ) or a subclock ( edge the next rising edge is called one state. A bus cycle consists of two states ...
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On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states, three states, or four states. The data bus width is 8 bits or 16 bits depending on the register. For description on the data bus width and number ...
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Section 2 CPU 2.7 CPU States There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active mode and subactive mode. For the program halt state, there are ...
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Reset cleared Reset state Reset occurs Reset occurs Reset occurs Program halt state SLEEP instruction executed Figure 2.12 State Transitions Exception-handling state Interrupt source Interrupt Exception- source handling complete Program execution state Rev. 4.00 Mar. 15, 2006 Page 41 of ...
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Section 2 CPU 2.8 Usage Notes 2.8.1 Notes on Data Access to Empty Areas The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip I/O registers areas available to the user. When data ...
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The timer is counting, so the value read is not necessarily the same as the value in the timer load register result, bits other than the intended bit in the timer counter may be modified and the modified ...
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Section 2 CPU After executing BSET instruction P57 P56 Input/output Input Input Pin state Low High level level PCR5 0 0 PDR5 0 1 Description on operation 1. When the BSET instruction is executed, first the CPU reads port 5. ...
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BSET instruction executed BSET #0, @RAM0 After executing BSET instruction MOV.B @RAM0, R0L MOV.B R0L, @PDR5 P57 P56 Input/output Input Input Pin state Low High level level PCR5 0 0 PDR5 1 0 RAM0 1 0 (2) Bit Manipulation in ...
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Section 2 CPU BCLR instruction executed BCLR #0, @PCR5 After executing BCLR instruction P57 P56 Input/output Output Output Pin state Low High level level PCR5 1 1 PDR5 1 0 Description on operation 1. When the BCLR instruction is executed, ...
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BCLR instruction executed BCLR #0, @RAM0 After executing BCLR instruction MOV.B @RAM0, R0L MOV.B R0L, @PCR5 P57 P56 Input/output Input Input Pin state Low High level level PCR5 0 0 PDR5 1 0 RAM0 0 0 The BCLR instructions executed ...
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Section 2 CPU Rev. 4.00 Mar. 15, 2006 Page 48 of 556 REJ09B0026-0400 ...
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Section 3 Exception Handling Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts. Reset A reset has the highest exception priority. Exception handling starts as soon as the reset is cleared by the RES pin. ...
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Section 3 Exception Handling 3.1 Exception Sources and Vector Address Table 3.1 shows the vector addresses and priority of each exception handling. When more than one interrupt is requested, handling is performed from the interrupt with the highest priority. Table ...
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Relative Module Exception Sources Timer Z Compare match/input capture Timer Z overflow Compare match/input capture Timer Z overflow Timer Z underflow Timer B1 Timer B1 overflow 2 SCI3_2* Receive data full Transmit data empty ...
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Section 3 Exception Handling 3.2 Register Descriptions Interrupts are controlled by the following registers. Interrupt edge select register 1 (IEGR1) Interrupt edge select register 2 (IEGR2) Interrupt enable register 1 (IENR1) Interrupt enable register 2 (IENR2) Interrupt flag register 1 ...
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Interrupt Edge Select Register 2 (IEGR2) IEGR2 selects the direction of an edge that generates interrupt requests of the pins ADTRG and WKP5 to WKP0. Initial Bit Bit Name Value 7, 6 All 1 5 WPEG5 0 4 WPEG4 ...
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Section 3 Exception Handling 3.2.3 Interrupt Enable Register 1 (IENR1) IENR1 enables direct transition interrupts and external pin interrupts. Initial Bit Bit Name Value 7 IENDT IENWP IEN3 0 2 IEN2 0 ...
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Interrupt Enable Register 2 (IENR2) IENR2 enables, timer B1 overflow interrupts. Initial Bit Bit Name Value 7, 6 All 0 5 IENTB1 All 1 When disabling interrupts by clearing bits in an interrupt enable register, ...
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Section 3 Exception Handling Initial Bit Bit Name Value 3 IRRI3 0 2 IRRI2 0 1 IRRI1 0 0 IRRl0 0 Rev. 4.00 Mar. 15, 2006 Page 56 of 556 REJ09B0026-0400 R/W Description R/W IRQ3 Interrupt Request Flag [Setting condition] ...
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Interrupt Flag Register 2 (IRR2) IRR2 is a status flag register for timer B1 overflow interrupts. Initial Bit Bit Name Value 7, 6 All 0 5 IRRTB1 All 1 3.2.7 Wakeup Interrupt Flag Register (IWPR) ...
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Section 3 Exception Handling Initial Bit Bit Name Value 3 IWPF3 0 2 IWPF2 0 1 IWPF1 0 0 IWPF0 0 Rev. 4.00 Mar. 15, 2006 Page 58 of 556 REJ09B0026-0400 R/W Description R/W WKP3 Interrupt Request Flag [Setting condition] ...
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Reset Exception Handling When the RES pin goes low, all processing halts and this LSI enters the reset. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized by the reset. To ensure ...
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Section 3 Exception Handling 3.4 Interrupt Exception Handling 3.4.1 External Interrupts As the external interrupts, there are NMI, IRQ3 to IRQ0, and WKP5 to WKP0 interrupts. NMI Interrupt: NMI interrupt is requested by input signal edge to pin NMI. This ...
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RES Internal address bus Internal read signal Internal write signal Internal data bus (16 bits) (1) Reset exception handling vector address (H'0000) (2) Program start address (3) Initial program instruction 3.4.2 Internal Interrupts Each on-chip peripheral module has a flag ...
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Section 3 Exception Handling 3.4.3 Interrupt Handling Sequence Interrupts are controlled by an interrupt controller. Interrupt operation is described as follows interrupt occurs while the NMI or interrupt enable bit is set interrupt request ...
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SP – – – – (R7) Stack area Prior to start of interrupt exception handling [Legend Upper 8 bits of program counter (PC Lower 8 bits ...
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Section 3 Exception Handling Rev. 4.00 Mar. 15, 2006 Page 64 of 556 REJ09B0026-0400 Figure 3.3 Interrupt Sequence ...
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Usage Notes 3.5.1 Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, ...
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Section 3 Exception Handling Rev. 4.00 Mar. 15, 2006 Page 66 of 556 REJ09B0026-0400 ...
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Section 4 Address Break The address break simplifies on-board program debugging. It requests an address break interrupt when the set break condition is satisfied. The interrupt request is not affected by the I bit in CCR. Break conditions that can ...
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Section 4 Address Break 4.1 Register Descriptions The address break has the following registers. Address break control register (ABRKCR) Address break status register (ABRKSR) Break address register (BARH, BARL) Break data register (BDRH, BDRL) 4.1.1 Address Break Control Register (ABRKCR) ...
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Initial Bit Bit Name Value 1 DCMP1 0 0 DCMP0 0 [Legend] X: Don't care. When an address break is set in the data read cycle or data write cycle, the data bus used will depend on the combination of ...
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Section 4 Address Break 4.1.2 Address Break Status Register (ABRKSR) ABRKSR consists of the address break interrupt flag and the address break interrupt enable bit. Initial Bit Bit Name Value 7 ABIF 0 6 ABIE — ...
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Operation When the ABIF and ABIE bits in ABRKSR are set to 1, the address break function generates an interrupt request to the CPU. The ABIF bit in ABRKSR is set the combination of the address ...
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Section 4 Address Break When the address break is specified in the data read cycle Register setting • ABRKCR = H'A0 • BAR = H'025A MOV instruc- tion 1 prefetch Address 025C bus Interrupt request Figure 4.2 Address Break Interrupt ...
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Section 5 Clock Pulse Generators The clock pulse generator is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator, a duty correction circuit, and ...
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Section 5 Clock Pulse Generators 5.1 System Clock Generator Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic resonator providing external clock input. Figure 5.2 shows a block diagram of ...
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Table 5.1 Crystal Resonator Parameters Frequency (MHz (max) 500 S C (max 5.1.2 Connecting Ceramic Resonator Figure 5.5 shows a typical method of connecting a ceramic resonator. OSC OSC Figure 5.5 Typical Connection to Ceramic ...
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Section 5 Clock Pulse Generators 5.2 Prescaler 5.2.1 Prescaler S Prescaler 13-bit counter using the system clock ( ) as its input clock incremented once per clock period. Prescaler S is initialized to H'0000 by ...
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Section 6 Power-Down Modes This LSI has six modes of operation after a reset. These include a normal active mode and four power-down modes, in which power consumption is significantly reduced. Module standby mode reduces power consumption by selectively halting ...
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Section 6 Power-Down Modes 6.1 Register Descriptions The registers related to power-down modes are listed below. System control register 1 (SYSCR1) System control register 2 (SYSCR2) Module standby control register 1 (MSTCR1) Module standby control register 2 (MSTCR2) 6.1.1 System ...
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Table 6.1 Operating Frequency and Waiting Time Bit Name STS2 STS1 STS0 Waiting Time 8,192 states 1 16,384 states 1 0 32,768 states 1 65,536 states 131,072 states 1 1,024 states 1 0 128 ...
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Section 6 Power-Down Modes Initial Bit Bit Name Value 1 SA1 0 0 SA0 0 [Legend] X: Don't care. 6.1.3 Module Standby Control Register 1 (MSTCR1) MSTCR1 allows the on-chip peripheral modules to enter a standby state in module units. ...
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Module Standby Control Register 2 (MSTCR2) MSTCR2 allows the on-chip peripheral modules to enter a standby state in module units. Initial Bit Bit Name Value 7 MSTS3_2 All 0 4 MSTTB1 All 0 ...
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Section 6 Power-Down Modes 6.2 Mode Transitions and States of LSI Figure 6.1 shows the possible transitions among these operating modes. A transition is made from the program execution state to the program halt state by executing a SLEEP instruction. ...
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Table 6.2 Transition Mode after SLEEP Instruction Execution and Transition Mode due to Interrupt DTON SSBY SMSEL [Legend] X: Don’t care. Note: When a state transition is made while ...
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Section 6 Power-Down Modes Function Active Mode Peripheral Timer V Functioning functions Watchdog Functioning timer 2 SCI3, SCI3_2* Functioning TinyCAN Functioning SSU Functioning Subtimer Functioning Timer B1 Functioning Timer Z Functioning A/D converter Functioning Note: Registers can be read from ...
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Standby mode is cleared by an interrupt. When an interrupt is requested, the system clock pulse generator starts. After the time set in bits STS2 to STS0 in SYSCR1 has elapsed, and interrupt exception handling starts. Standby mode is not ...
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Section 6 Power-Down Modes 6.3 Operating Frequency in Active Mode Operation in active mode is clocked at the frequency designated by the MA2, MA1, and MA0 bits in SYSCR2. The operating frequency changes to the set frequency after SLEEP instruction ...
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Direct Transition from Subactive Mode to Active Mode The time from the start of SLEEP instruction execution to the end of interrupt exception handling (the direct transition time) is calculated by equation (2). Direct transition time = {(number of ...
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Section 6 Power-Down Modes Rev. 4.00 Mar. 15, 2006 Page 88 of 556 REJ09B0026-0400 ...
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The features of the 56-kbyte or 32-kbyte flash memories built into the flash memory (F-ZTAT) version are summarized below. Programming/erase methods The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units. The flash memory ...
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Section 7 ROM H'0000 Erase unit H'0080 1 kbyte H'0380 H'0400 Erase unit H'0480 1 kbyte H'0780 H'0800 Erase unit H'0880 1 kbyte H'0B80 H'0C00 Erase unit H'0C80 1 kbyte H'0F80 H'1000 Erase unit H'1080 28 kbytes H'7F80 H'8000 Erase ...
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Register Descriptions The flash memory has the following registers. Flash memory control register 1 (FLMCR1) Flash memory control register 2 (FLMCR2) Erase block register 1 (EBR1) Flash memory power control register (FLPWCR) Flash memory enable register (FENR) 7.2.1 Flash ...
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Section 7 ROM Initial Bit Bit Name Value 7.2.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a read-only ...
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Erase Block Register 1 (EBR1) EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit in FLMCR1 not set more than one bit at a time, as this will ...
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Section 7 ROM 7.2.4 Flash Memory Power Control Register (FLPWCR) FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI switches to subactive mode. There are two modes: mode in which operation of the power ...
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On-Board Programming Modes There are two modes for programming/erasing of the flash memory; boot mode, which enables on- board programming/erasing, and programmer mode, in which programming/erasing is performed with a PROM programmer. On-board programming/erasing can also be performed in ...
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Section 7 ROM 7.3.1 Boot Mode Table 7.2 shows the boot mode operations between reset end and branching to the programming control program. 1. When boot mode is used, the flash memory programming control program must be prepared in the ...
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Table 7.2 Boot Mode Operation Host Operation Processing Contents Continuously transmits data H'00 at specified bit rate. Transmits data H'55 when data H'00 is received error-free. Boot program erase error H'AA reception Transmits number of bytes (N) of programming control ...
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Section 7 ROM Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible Host Bit Rate System Clock Frequency Range of LSI 19,200 bps MHz 9,600 bps MHz 4,800 ...
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Reset-start Program/erase? Yes Transfer user program/erase control program to RAM Branch to user program/erase control program in RAM Execute user program/erase control program (flash memory rewrite) Branch to flash memory application program Figure 7.2 Programming/Erasing Flowchart Example in User Program ...
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Section 7 ROM 7.4 Flash Memory Programming/Erasing A software method using the CPU is employed to program and erase flash memory in the on- board programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the ...
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The maximum number of repetitions of the program/program-verify sequence of the same bit is 1,000. Write pulse application subroutine Apply Write Pulse WDT enable Set PSU bit in FLMCR1 Wait 50 s Set P bit in FLMCR1 Wait (Wait ...
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Section 7 ROM Table 7.4 Reprogram Data Computation Table Program Data Verify Data Table 7.5 Additional-Program Data Computation Table Reprogram Data Verify Data Table ...
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Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 7.4 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification ...
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Section 7 ROM Increment address Note: * The RTS instruction must not be used during a period between dummy writing of H' verify address and verify data reading. Figure 7.4 Erase/Erase-Verify Flowchart Rev. 4.00 Mar. 15, 2006 Page ...
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Program/Erase Protection There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 7.5.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because ...
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Section 7 ROM The FLMCR1, FLMCR2, and EBR1 settings are retained, however program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be re- entered by re-setting the P ...
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Table 7.7 Flash Memory Operating States LSI Operating State Active mode Subactive mode Sleep mode Subsleep mode Standby mode Flash Memory Operating State PDWND = 0 (Initial Value) Normal operating mode Power-down mode Normal operating mode Standby mode Standby mode ...
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Section 7 ROM Rev. 4.00 Mar. 15, 2006 Page 108 of 556 REJ09B0026-0400 ...
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This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling two-state access by the CPU to both byte data and word data. Product Classification Flash memory version H8/36057F, H8/36037F ...
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Section 8 RAM Rev. 4.00 Mar. 15, 2006 Page 110 of 556 REJ09B0026-0400 ...
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This LSI has forty-five general I/O ports and eight general input-only ports. Port large current port, which can drive 20 mA (@V these ports can become an input port immediately after a reset. They can also be ...
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Section 9 I/O Ports 9.1.1 Port Mode Register 1 (PMR1) PMR1 switches the functions of pins in port 1 and port 2. Initial Bit Bit Name Value 7 IRQ3 0 6 IRQ2 0 5 IRQ1 0 4 IRQ0 0 3 ...
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Port Control Register 1 (PCR1) PCR1 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 1. Initial Bit Bit Name Value 7 PCR17 0 6 PCR16 0 5 PCR15 0 4 PCR14 ...
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Section 9 I/O Ports 9.1.4 Port Pull-Up Control Register 1 (PUCR1) PUCR1 controls the pull-up MOS in bit units of the pins set as the input ports. Initial Bit Bit Name Value 7 PUCR17 0 6 PUCR16 0 5 PUCR15 ...
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P16/IRQ2 pin Register PMR1 PCR1 Bit Name IRQ2 PCR16 Setting value [Legend] X: Don't care. P15/IRQ1/TMIB1 pin Register PMR1 PCR1 Bit Name IRQ1 PCR15 Setting value [Legend] X: Don't care. ...
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Section 9 I/O Ports P11 pin Register PCR1 Bit Name PCR11 Pin Function Setting value 0 P11 input pin 1 P11 output pin P10 pin Register PCR1 Bit Name PCR10 Pin Function Setting value 0 P10 input pin 1 P10 ...
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Port Control Register 2 (PCR2) PCR2 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 2. Initial Bit Bit Name Value PCR24 0 3 PCR23 0 2 PCR22 ...
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Section 9 I/O Ports 9.2.3 Port Mode Register 3 (PMR3) PMR3 selects the CMOS output or NMOS open-drain output for port 2. Initial Bit Bit Name Value All 0 4 POF24 0 3 POF23 ...
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P22/TXD pin Register PMR1 PCR2 Bit Name TXD PCR22 Setting Value [Legend] X: Don't care. P21/RXD pin Register SCR3 PCR2 Bit Name RE PCR21 Setting Value [Legend] X: Don't care. ...
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Section 9 I/O Ports 9.3 Port 5 Port general I/O port also functioning as an A/D trigger input pin and a wakeup interrupt input pin. Each pin of the port 5 is shown in figure 9.3. The ...
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Port Mode Register 5 (PMR5) PMR5 switches the functions of pins in port 5. Initial Bit Bit Name Value 7 POF57 0 6 POF56 0 5 WKP5 0 4 WKP4 0 3 WKP3 0 2 WKP2 0 1 WKP1 ...
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Section 9 I/O Ports 9.3.2 Port Control Register 5 (PCR5) PCR5 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 5. Initial Bit Bit Name Value 7 PCR57 0 6 PCR56 0 5 ...
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Port Pull-Up Control Register 5 (PUCR5) PUCR5 controls the pull-up MOS in bit units of the pins set as the input ports. Initial Bit Bit Name Value 7, 6 All 0 5 PUCR55 0 4 PUCR54 0 3 PUCR53 ...
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Section 9 I/O Ports P55/WKP5/ADTRG pin Register PMR5 PCR5 Bit Name WKP5 PCR55 Setting Value [Legend] X: Don't care. P54/WKP4 pin Register PMR5 PCR5 Bit Name WKP4 PCR54 Setting Value ...
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P52/WKP2 pin Register PMR5 PCR5 Bit Name WKP2 PCR52 Setting Value [Legend] X: Don't care. P51/WKP1 pin Register PMR5 PCR5 Bit Name WKP1 PCR51 Setting Value [Legend] X: Don't care. ...
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Section 9 I/O Ports 9.4 Port 6 Port general I/O port also functioning as a timer Z I/O pin. Each pin of the port 6 is shown in figure 9.4. The register setting of the timer Z ...
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Port Data Register 6 (PDR6) PDR6 is a general I/O port data register of port 6. Initial Bit Bit Name Value 7 P67 0 6 P66 0 5 P65 0 4 P64 0 3 P63 0 2 P62 0 ...
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Section 9 I/O Ports P66/FTIOC1 pin Register TOER TFCR CMD1, Bit Name EC1 CMD0 Setting Value Other than 00 [Legend] X: Don't care. P65/FTIOB1 pin Register TOER TFCR CMD1, Bit Name EB1 CMD0 Setting Value 1 ...
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P64/FTIOA1 pin Register TOER TFCR CMD1, Bit Name EB1 CMD0 Setting Value [Legend] X: Don't care. P63/FTIOD0 pin Register TOER TFCR CMD1, Bit Name ED0 CMD0 Setting Value Other than 00 [Legend] ...
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Section 9 I/O Ports P62/FTIOC0 pin Register TOER TFCR CMD1, Bit Name EC0 CMD0 Setting Value Other than 00 [Legend] X: Don't care. P61/FTIOB0 pin Register TOER TFCR CMD1, Bit Name EB0 CMD0 Setting Value 1 ...
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P60/FTIOA0 pin Register TOER TFCR CMD1, Bit Name EA0 CMD0 Setting Value [Legend] X: Don't care. 9.5 Port 7 Port general I/O port also functioning as a timer V I/O pin and SCI3_2 ...
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Section 9 I/O Ports 9.5.1 Port Control Register 7 (PCR7) PCR7 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 7. Initial Bit Bit Name Value 7 6 PCR76 0 5 PCR75 0 ...
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Pin Functions The correspondence between the register specification and the port functions is shown below. P76/TMOV pin Register TCSRV Bit Name OS3 to OS0 PCR76 Setting Value 0000 Other than the above values [Legend] X: Don't care. P75/TMCIV pin ...
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Section 9 I/O Ports P72/TXD_2* pin Register PMR1* PCR7 Bit Name TXD2* PCR72 Setting Value [Legend] X: Don't care. Note: The H8/36037 Group does not have this pin. * P71/RXD_2* pin Register SCR3_2* PCR7 Bit ...
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Port 8 Port general I/O port. Each pin of the port 8 is shown in figure 9.6. Port 8 has the following registers. Port control register 8 (PCR8) Port data register 8 (PDR8) 9.6.1 Port Control ...
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Section 9 I/O Ports 9.6.2 Port Data Register 8 (PDR8) PDR8 is a general I/O port data register of port 8. Initial Bit Bit Name Value 7 P87 0 6 P86 0 5 P85 All 1 ...
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Port 9 Port general I/O port also functioning as a TinyCAN I/O pin and an SSU I/O pin. Each pin of the port 9 is shown in figure 9.7. Port 9 has the following registers. Port ...
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Section 9 I/O Ports 9.7.2 Port Data Register 9 (PDR9) PDR9 is a general I/O port data register of port 9. Initial Bit Bit Name Value 7 P97 0 6 P96 0 5 P95 0 4 P94 0 3 P93 ...
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P96/HRXD pin Register TCMR Bit Name PMR96 Setting Value 0 1 [Legend] X: Don't care. P95 pin Register PCR9 Bit Name PCR95 Setting Value 0 1 P94 pin Register PCR9 Bit Name PCR94 Setting Value 0 1 P93/SSI pin Register ...
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Section 9 I/O Ports P92/SSO pin Register PCR9 Bit Name PCR92 Setting Value [Legend] X: Don't care. Note: When this pin is used as the SSO pin, register settings of the SSU are required. For details, see ...
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Port B Port input port also functioning as an A/D converter analog input pin. Each pin of the port B is shown in figure 9.8. Port B has the following register. Port data register B (PDRB) ...
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Section 9 I/O Ports Rev. 4.00 Mar. 15, 2006 Page 142 of 556 REJ09B0026-0400 ...
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The timer 8-bit timer that increments each time a clock pulse is input. This timer has two operating modes, interval and auto reload. Figure 10.1 shows a block diagram of the timer B1. 10.1 Features Selection of ...
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Section 10 Timer B1 10.2 Input/Output Pin Table 10.1 shows the timer B1 pin configuration. Table 10.1 Pin Configuration Name Abbreviation Timer B1 event input TMIB1 Rev. 4.00 Mar. 15, 2006 Page 144 of 556 REJ09B0026-0400 I/O Function Input Event ...
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Register Descriptions The timer B1 has the following registers. Timer mode register B1 (TMB1) Timer counter B1 (TCB1) Timer load register B1 (TLB1) 10.3.1 Timer Mode Register B1 (TMB1) TMB1 selects the auto-reload function and input clock. Initial Bit ...
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Section 10 Timer B1 10.3.2 Timer Counter B1 (TCB1) TCB1 is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TMB12 to TMB10 in TMB1. TCB1 ...
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Operation 10.4.1 Interval Timer Operation When bit TMB17 in TMB1 is cleared to 0, timer B1 functions as an 8-bit interval timer. Upon reset, TCB1 is cleared to H'00 and bit TMB17 is cleared up-counting and ...
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Section 10 Timer B1 10.5 Timer B1 Operating Modes Table 10.2 shows the timer B1 operating modes. Table 10.2 Timer B1 Operating Modes Operating Mode Reset TCB1 Interval Reset Auto- Reset reload TMB1 Reset Rev. 4.00 Mar. 15, 2006 Page ...
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The timer 8-bit timer based on an 8-bit counter. The timer V counts external events. Compare-match signals with two registers can also be used to reset the counter, request an interrupt, or output a pulse signal with ...
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Section 11 Timer V TRGV Clock select TMCIV PSS TMRIV TMOV [Legend] TCORA: Time constant register A TCORB: Time constant register B TCNTV: Timer counter V TCSRV: Timer control/status register V TCRV0: Timer control register V0 TCRV1: Timer control register ...
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Input/Output Pins Table 11.1 shows the timer V pin configuration. Table 11.1 Pin Configuration Name Timer V output Timer V clock input Timer V reset input Trigger input 11.3 Register Descriptions The time V has the following registers. Timer ...
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Section 11 Timer V 11.3.2 Time Constant Registers A and B (TCORA, TCORB) TCORA and TCORB have the same function. TCORA and TCORB are 8-bit read/write registers. TCORA and TCNTV are compared at all times. When the TCORA and TCNTV ...
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Initial Bit Bit Name Value 2 CKS2 0 1 CKS1 0 0 CKS0 0 Table 11.2 Clock Signals to Input to TCNTV and Counting Conditions TCRV0 Bit 2 Bit 1 Bit 0 CKS2 CKS1 CKS0 ...
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Section 11 Timer V 11.3.4 Timer Control/Status Register V (TCSRV) TCSRV indicates the status flag and controls outputs by using a compare match. Initial Bit Bit Name Value 7 CMFB 0 6 CMFA 0 5 OVF ...
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Initial Bit Bit Name Value 1 OS1 0 0 OS0 0 OS3 and OS2 select the output level for compare match B. OS1 and OS0 select the output level for compare match A. The two output levels can be controlled ...
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Section 11 Timer V Initial Bit Bit Name Value ICKS0 0 11.4 Operation 11.4.1 Timer V Operation 1. According to table 11.2, six internal/external clock signals output by prescaler S can be selected as the timer V ...
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Internal clock TCNTV input clock N – 1 TCNTV Figure 11.2 Increment Timing with Internal Clock TMCIV (External clock input pin) TCNTV input clock N – 1 TCNTV Figure 11.3 Increment Timing with External Clock TCNTV H'FF Overflow signal OVF ...
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Section 11 Timer V TCNTV TCORA or TCORB Compare match signal CMFA or CMFB Figure 11.5 CMFA and CMFB Set Timing Compare match A signal Timer V output pin Compare match A signal TCNTV Figure 11.7 Clear Timing by Compare ...
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TMRIV (External counter reset pin) TCNTV reset signal TCNTV Figure 11.8 Clear Timing by TMRIV Input 11.5 Timer V Application Examples 11.5.1 Pulse Output with Arbitrary Duty Cycle Figure 11.9 shows an example of output of pulses with an arbitrary ...
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Section 11 Timer V 11.5.2 Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input The trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary delay from the TRGV input, as ...
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Usage Notes The following types of contention or operation can occur in timer V operation. 1. Writing to registers is performed in the T3 state of a TCNTV write cycle TCNTV clear signal is generated in the ...
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Section 11 Timer V Address Internal write signal TCNTV TCORA Compare match signal Figure 11.12 Contention between TCORA Write and Compare Match Clock before switching Clock after switching Count clock TCNTV Figure 11.13 Internal Clock Switching and TCNTV Operation Rev. ...
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The timer Z has a 16-bit timer with two channels. Figures 12.1, 12.2, and 12.3 show the block diagrams of entire timer Z, its channel 0, and its channel 1, respectively. For details on the timer Z functions, refer to ...
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Section 12 Timer Z Eleven interrupt sources Four compare match/input capture interrupts and an overflow interrupt are available for each channel. An underflow interrupt can be set for channel 1. Table 12.1 Timer Z Functions Item Channel 0 Count clock ...
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FTIOA0 FTIOB0 FTIOC0 FTIOD0 FTIOA1 FTIOB1 FTIOC1 FTIOD1 , /2, /4, /8 Channel 0 timer [Legend] TSTR : Timer start register (8 bits) TMDR : Timer mode register (8 bits) TPMR : Timer PWM mode register (8 bits) TFCR : ...
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Section 12 Timer Z , /2, Clock select /4, /8 Comparator [Legend] TCNT_0 : Timer counter_0 (16 bits) GRA_0, GRB_0, General registers A_0, B_0, C_0, and D_0 (input capture/output compare registers: 16 bits × 4) GRC_0, GRD_0 : TCR_0 : ...