DF36034GFPJ Renesas Electronics America, DF36034GFPJ Datasheet - Page 339
![MCU 3/5V 32K J-TEMP POR&LVD 64-L](/photos/28/61/286100/64-lqfp__plqp0064kb-a_sml.jpg)
DF36034GFPJ
Manufacturer Part Number
DF36034GFPJ
Description
MCU 3/5V 32K J-TEMP POR&LVD 64-L
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.DF36057GFZV.pdf
(594 pages)
Specifications of DF36034GFPJ
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F36034GFPJ
HD64F36034GFPJ
HD64F36034GFPJ
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Bit
6
5
4
3
2
1
0
Bit Name
TSG22
TSG21
TSG20
TSG13
TSG12
TSG11
TSG10
Initial
Value
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Time Segment 2
This segment is used for correcting the error of 1 bit time.
The TSG2 width can be set within a range of 2 to 8 time
quanta.
000: Setting prohibited
001: PHSEG2 = 2 time quanta
010: PHSEG2 = 3 time quanta
011: PHSEG2 = 4 time quanta
100: PHSEG2 = 5 time quanta
101: PHSEG2 = 6 time quanta
110: PHSEG2 = 7 time quanta
111: PHSEG2 = 8 time quanta
Time Segment 1
This segment is used for absorbing the delay of the
output buffer, CAN bus, and input buffer. The TSG1 width
can be set within a range of 1 to 16 time quanta. TSG1
comprises PRSEG and PHSEG1 according to the CAN
specifications.
0000: Setting prohibited
0001: Setting prohibited
0010: Setting prohibited
0011: PRSEG + PHSEG1 = 4 time quanta
1111: PRSEG + PHSEG1 = 16 time quanta
Section 15 Controller Area Network for Tiny (TinyCAN)
:
Rev. 4.00 Mar. 15, 2006 Page 305 of 556
REJ09B0026-0400
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