DF36034GFPJ Renesas Electronics America, DF36034GFPJ Datasheet - Page 385

• Manufacturer Part Number: DF36034GFPJ
• Description: MCU 3/5V 32K J-TEMP POR&LVD 64-L
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of DF36034GFPJ

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SSU
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F36034GFPJ; HD64F36034GFPJ

16.3.1
SSCRH is a register that selects a master or a slave device, enables bidirectional mode, selects
open-drain output of the serial data output pin, selects an output value of the serial data output pin,
selects the SSCK pin, and selects the SCS pin.
Bit
7
6
5
Bit Name
MSS
BIDE
SOOS
SS Control Register H (SSCRH)
Initial
Value
0
0
0
R/W
R/W
R/W
R/W
Description
Master/Slave Device Select
Selects whether this module is used as a master device
or a slave device. When this module is used as a master
device, transfer clock is output from the SSCK pin. When
the CE bit in SSSR is set, this bit is automatically cleared.
0: Operates as a slave device
1: Operates as a master device
Bidirectional Mode Enable
Selects whether the serial data input pin and the output
pin are both used or only one pin is used. For details,
refer to section 16.4.3, Relationship between Data
Input/Output Pin and Shift Register. When the SSUMS bit
in SSCRL is 0, this setting is invalid.
0: Normal mode. Communication is performed by using
1: Bidirectional mode. Communication is performed by
Serial Data Open-Drain Output Select
Selects whether the serial data output pin is CMOS
output or NMOS open-drain output. The serial data output
pin is changed according to the register setting value. For
details, refer to section 16.4.3, Relationship between
Data Input/Output Pin and Shift Register.
0: CMOS output
1: NMOS open-drain output
two pins.
using only one pin.
Section 16 Synchronous Serial Communication Unit (SSU)
Rev. 4.00 Mar. 15, 2006 Page 351 of 556
REJ09B0026-0400