DF36034GFPJ Renesas Electronics America, DF36034GFPJ Datasheet - Page 256
![MCU 3/5V 32K J-TEMP POR&LVD 64-L](/photos/28/61/286100/64-lqfp__plqp0064kb-a_sml.jpg)
DF36034GFPJ
Manufacturer Part Number
DF36034GFPJ
Description
MCU 3/5V 32K J-TEMP POR&LVD 64-L
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.DF36057GFZV.pdf
(594 pages)
Specifications of DF36034GFPJ
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F36034GFPJ
HD64F36034GFPJ
HD64F36034GFPJ
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Section 12 Timer Z
Complementary PWM Mode: When the counter switches from counting up to counting down or
vice versa, the value of the buffer register is transferred to the general register. Here, the value of
the buffer register is transferred to the general register in the following timing:
1. When TCNT_0 and GRA_0 are compared and their contents match
2. When TCNT_1 underflows
Reset Synchronous PWM Mode: The value of the buffer register is transferred from compare
match A0 to the general register.
Example of Buffer Operation Setting Procedure: Figure 12.37 shows an example of the buffer
operation setting procedure.
Rev. 4.00 Mar. 15, 2006 Page 222 of 556
REJ09B0026-0400
Start count operation
Set buffer operation
Select GR function
<Buffer operation>
Figure 12.37 Example of Buffer Operation Setting Procedure
Buffer operation
[1]
[2]
[3]
[1] Designate GR as an input capture register
[2] Designate GR for buffer operation with bits
[3] Set the STR bit in TSTR to 1 to start the
or output compare register by means of
TIOR.
BFD1, BFC1, BFD0, or BFC0 in TMDR.
count operation of TCNT.
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