DF36034GFPJ Renesas Electronics America, DF36034GFPJ Datasheet - Page 215
![MCU 3/5V 32K J-TEMP POR&LVD 64-L](/photos/28/61/286100/64-lqfp__plqp0064kb-a_sml.jpg)
DF36034GFPJ
Manufacturer Part Number
DF36034GFPJ
Description
MCU 3/5V 32K J-TEMP POR&LVD 64-L
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.DF36057GFZV.pdf
(594 pages)
Specifications of DF36034GFPJ
Core Processor
H8/300H
Core Size
16-Bit
Speed
20MHz
Connectivity
CAN, SCI, SSU
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
45
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F36034GFPJ
HD64F36034GFPJ
HD64F36034GFPJ
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[Legend]
X: Don't care
TIORC: TIORC selects whether GRC or GRD is used as an output compare register or an input
capture register. When an output compare register is selected, the output setting is selected. When
an input capture register is selected, an input edge of an input capture signal is selected. TIORC
also selects the function of FTIOC or FTIOD pin.
Bit
2
1
0
Bit
7
6
5
4
3
Bit Name
IOA2
IOA1
IOA0
Bit Name
IOD2
IOD1
IOD0
Initial
Value
0
0
0
Initial
Value
1
0
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
I/O Control A2 to A0
GRA is an output compare register:
000: Disables pin output by compare match
001: 0 output by GRA compare match
010: 1 output by GRA compare match
011: Toggle output by GRA compare match
GRA is an input capture register:
100: Input capture to GRA at the rising edge
101: Input capture to GRA at the falling edge
11X: Input capture to GRA at both rising and falling edges
Description
Reserved
This bit is always read as 1.
I/O Control D2 to D0
GRD is an output compare register:
000: Disables pin output by compare match
001: 0 output by GRD compare match
010: 1 output by GRD compare match
011: Toggle output by GRD compare match
GRD is an input capture register:
100: Input capture to GRD at the rising edge
101: Input capture to GRD at the falling edge
11X: Input capture to GRD at both rising and falling edges
Reserved
This bit is always read as 1.
Rev. 4.00 Mar. 15, 2006 Page 181 of 556
Section 12 Timer Z
REJ09B0026-0400
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