DF36034GFPJ Renesas Electronics America, DF36034GFPJ Datasheet - Page 444

• Manufacturer Part Number: DF36034GFPJ
• Description: MCU 3/5V 32K J-TEMP POR&LVD 64-L
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of DF36034GFPJ

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: CAN, SCI, SSU
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F36034GFPJ; HD64F36034GFPJ

Section 19 Power-On Reset and Low-Voltage Detection Circuits (Optional)
LVDI (Interrupt by Low Voltage Detect) Circuit:
Figure 19.4 shows the timing of LVDI functions. The LVDI enters the module-standby state after
a power-on reset is canceled. To operate the LVDI, set the LVDE bit in LVDCR to 1, wait for 50
by a software timer, etc., then set the LVDDE and LVDUE bits in LVDCR to 1. After that, the
output settings of ports must be made. To cancel the low-voltage detection circuit, first the
LVDDE and LVDUE bits should all be cleared to 0 and then the LVDE bit should be cleared to 0.
The LVDE bit must not be cleared to 0 at the same timing as the LVDDE and LVDUE bits
because incorrect operation may occur.
When the power-supply voltage falls below Vint (D) (typ. = 3.7 V) voltage, the LVDI clears the
LVDINT signal to 0 and the LVDDF bit in LVDSR is set to 1. If the LVDDE bit is 1 at this time,
an IRQ0 interrupt request is simultaneously generated. In this case, the necessary data must be
saved in the external EEPROM, etc, and a transition must be made to standby mode or subsleep
mode. Until this processing is completed, the power supply voltage must be higher than the lower
limit of the guaranteed operating voltage.
When the power-supply voltage does not fall below Vreset1 (typ. = 2.3 V) voltage but rises above
Vint (U) (typ. = 4.0 V) voltage, the LVDI sets the LVDINT signal to 1. If the LVDUE bit is 1 at
Rev. 4.00 Mar. 15, 2006 Page 410 of 556
REJ09B0026-0400
s (t
LVDON
V
LVDRES
V
PSS-reset
signal
OVF
Internal reset
signal
LVDRmin
) until the reference voltage and the low-voltage-detection power supply have stabilized
CC
Figure 19.3 Operational Timing of LVDR Circuit
PSS counter starts
131,072 cycles
Reset released
Vreset
V
SS