MCF5214CVF66J Freescale Semiconductor, MCF5214CVF66J Datasheet - Page 293
MCF5214CVF66J
Manufacturer Part Number
MCF5214CVF66J
Description
IC MCU 256K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF521xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5214CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
142
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF521x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
M52210DEMO, M52211EVB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5214CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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The DACRs should be programmed as shown in
This configuration results in a value of DACR0 = 0xFF88_0300, as described in
initialization is not needed because there is only one block. Subsequently, DACR1[RE,IMRS,IP] should
be cleared; everything else is a don’t care.
Freescale Semiconductor
1 Mbyte
Setting
Setting
(hex)
(hex)
Field
Field RE
31–18
17–16
13–12
10–8
31
15
Bits
5–4
15
14
11
7
6
512 Kbyte
512 Kbyte
Bank 0
—
14
Name
CASL
IMRS
CBM
F
BA
RE
PS
—
—
—
—
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
13
CASL
1 Mbyte
1111_1111_
12
1000_10
Figure 15-13. DACR Register Configuration
Setting
011
00
00
Table 15-28. DACR Initialization Values
0
0
Figure 15-12. SDRAM Configuration
—
11
Base address. So DACR0[31–16] = 0xFF88, placing the starting
address of the SDRAM accessible memory at 0xFF88_0000.
Reserved. Don’t care.
Keeps auto-refresh disabled because registers are being set up
at this time.
Reserved. Don’t care.
Indicates a delay of data 1 cycle after SCAS is asserted
Reserved. Don’t care.
Command bit is pin 20 and bank selects are 21 and up.
Reserved. Don’t care.
Indicates
32-bit port.
512 Kbyte
512 Kbyte
10
Bank 1
SDRAM Component
F
CBM
1111_1111_1000_10xx
0000_x011_x000_0000
MRS
Figure
BA
1 Mbyte
command has not been initiated.
8
0300
15-13.
—
7
Description
IMRS
6
512 Kbyte
512 Kbyte
Bank 2
8
5
PS
Synchronous DRAM Controller Module
4
1 Mbyte
Accessible
Memory
IP
3
Table
18
2
512 Kbyte
512 Kbyte
15-28. DACR1
8
Bank 3
—
17
1
—
16
0
15-21
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