MCF5214CVF66J Freescale Semiconductor, MCF5214CVF66J Datasheet - Page 504

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MCF5214CVF66J

Manufacturer Part Number
MCF5214CVF66J
Description
IC MCU 256K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF521xr
Datasheet

Specifications of MCF5214CVF66J

Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
142
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF521x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
M52210DEMO, M52211EVB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCF5214CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
General Purpose I/O Module
26.1.1
The ports module controls the configuration for various external pins, including those used for:
26.1.2
The ports includes these distinctive features:
26.1.3
The operational modes for the ports are listed below. For more detailed descriptions of each mode, refer
to
26.2
The ports control the functionality of several external pins. These pins are listed in
26-4
Section 26.4, “Functional
External bus accesses
Chip selects
Debug data
Processor status
Ethernet data and control (not present on the MCF5214 and MCF5216)
FlexCAN transmit/receive data
I
QSPI
SDRAM control
32-bit DMA timers
UART transmit/receive
Control of primary function use on all ports
Digital I/O support for all ports
— Registers for storing output pin data
— Registers for controlling pin data direction
— Registers for reading current pin state
— Registers for setting and clearing output pin data registers
Single-chip mode
All pins are configured as digital I/O by default, except for debug data pins (DDATA[3:0]) and
processor status pins (PST[3:0]).
Master mode
Ports A and B function as the upper external data bus. Ports C and D can function as the lower
external data bus. Ports E–J are configured to support external memory.
2
C serial control
External Signal Description
Overview
Features
Modes of Operation
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Description.”
Table
Freescale Semiconductor
26-1.

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