MCF5214CVF66J Freescale Semiconductor, MCF5214CVF66J Datasheet - Page 611

• Manufacturer Part Number: MCF5214CVF66J
• Description: IC MCU 256K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5214CVF66J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF521x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: M52210DEMO, M52211EVB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

29.4.1
The RCR allows software control for requesting a reset, for independently asserting the external RSTO
pin, and for controlling low-voltage detect (LVD) functions.
Freescale Semiconductor
Bit(s)
7
6
5
4
Reset Control Register (RCR)
1
2
IPSBAR Offset
FRCRSTOUT
S/U = supervisor or user mode access.
Writes to reserved address locations have no effect and reads return 0s.
Address
SOFTRST
0x11_0000
0x11_0001
0x11_0002
0x11_0003
Reset
Name
Field SOFTRST FRCRSTOUT
LVDF
R/W
—
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
7
Allows software to request a reset. The reset caused by setting this bit clears this bit.
1 Software reset request
0 No software reset request
Allows software to assert or negate the external RSTO pin.
1 Assert RSTO pin
0 Negate RSTO pin
CAUTION: External logic driving reset configuration data during reset needs to be
considered when asserting the RSTO pin when setting FRCRSTOUT.
Reserved, should be cleared.
LVD flag. Indicates the low-voltage detect status if LVDE is set. Write a 1 to clear the
LVDF bit.
1 Low voltage has been detected
0 Low voltage has not been detected
NOTE: The setting of this flag causes an LVD interrupt if LVDE and LVDIE bits are set
and LVDRE is cleared when the supply voltage V
vector for this interrupt is shared with INT0 of the EPORT module. Interrupt arbitration
in the interrupt service routine is necessary if both of these interrupts are enabled.
Also, LVDF is not cleared at reset, however it will always initialize to a zero since the
part will not come out of reset while in a low-power state (LVDE/LVDRE bits are
enabled out of reset).
Figure 29-2. Reset Control Register (RCR)
Table 29-2. Reset Controller Memory Map
Table 29-3. RCR Field Descriptions
6
Reserved
Reserved
IPSBAR + 0x11_0000
Bits 7:0
—
5
RCR
RSR
0000_0101
LVDF
R/W
2
2
4
Description
LVDIE LVDRE
DD
drops below V
—
Access
S/U
S/U
—
—
DD
LVDE
Reset Controller Module
1
(minimum). The
0
29-3