MCF5214CVF66J Freescale Semiconductor, MCF5214CVF66J Datasheet - Page 443

• Manufacturer Part Number: MCF5214CVF66J
• Description: IC MCU 256K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5214CVF66J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF521x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: M52210DEMO, M52211EVB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

23.4.3.1
In automatic echo mode, shown in
The local CPU-to-receiver communication continues normally, but the CPU-to-transmitter link is
disabled. In this mode, received data is clocked on the receiver clock and re-sent on UTXDn. The receiver
must be enabled, but the transmitter need not be.
Because the transmitter is inactive, USRn[TXEMP,TXRDY] is inactive and data is sent as it is received.
Received parity is checked but not recalculated for transmission. Character framing is also checked, but
stop bits are sent as they are received. A received break is echoed as received until the next valid start bit
is detected.
23.4.3.2
Figure 23-22
mode is for testing the operation of a UART by sending data to the transmitter and checking data
assembled by the receiver to ensure proper operations.
Features of this local loopback mode are:
23.4.3.3
In remote loopback mode, shown in
bit on the UTXDn output. The local CPU-to-transmitter link is disabled. This mode is useful in testing
receiver and transmitter operation of a remote UART. For this mode, transmitter uses the receiver clock.
Because the receiver is not active, received data cannot be read by the CPU and all status conditions are
inactive. Received parity is not checked and is not recalculated for transmission. Stop bits are sent as they
are received. A received break is echoed as received until next valid start bit is detected.
Freescale Semiconductor
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Transmitter and CPU-to-receiver communications continue normally in this mode.
URXDn input data is ignored.
UTXDn is held marking.
The receiver is clocked by the transmitter clock. The transmitter must be enabled, but the receiver
need not be.
Automatic Echo Mode
Local Loopback Mode
Remote Loopback Mode
shows how UTXDn and URXDn are internally connected in local loopback mode. This
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
CPU
CPU
Disabled
Figure
Figure
Figure 23-22. Local Loopback
Figure 23-21. Automatic Echo
23-21, the UART automatically resends received data bit by bit.
Rx
23-23, the UART automatically transmits received data bit by
Rx
Tx
Tx
Disabled
Disabled
Disabled
URXDn Input
UTXDn Output
URXDn Input
URXDn Input
UTXDn Output
UART Modules
23-23