MCF5214CVF66J Freescale Semiconductor, MCF5214CVF66J Datasheet - Page 310

• Manufacturer Part Number: MCF5214CVF66J
• Description: IC MCU 256K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5214CVF66J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF521x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: M52210DEMO, M52211EVB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

DMA Controller Module
If DSIZE is another size, data writes are optimized to write the largest size allowed based on the address,
but not exceeding the configured size.
16.5.4.2 Bandwidth Control
Bandwidth control makes it possible to force the DMA off the bus to allow access to another device.
DCRn[BWC] provides seven levels of block transfer sizes. If the BCRn decrements to a multiple of the
decode of the BWC, the DMA bus request negates until the bus cycle terminates. If a request is pending,
the arbiter may then pass bus mastership to another device. If auto-alignment is enabled, DCRn[AA] = 1,
the BCRn may skip over the programmed boundary, in which case, the DMA bus request is not negated.
If BWC = 000, the request signal remains asserted until BCRn reaches zero. DMA has priority over the
core. Note that in this scheme, the arbiter can always force the DMA to relinquish the bus. See
Section 8.5.3, “Bus Master Park Register
16.5.5
An unsuccessful transfer can terminate for one of the following reasons:
16-14
•
•
•
Error conditions—When the processor encounters a read or write cycle that terminates with an
error condition, DSRn[BES] is set for a read and DSRn[BED] is set for a write before the transfer
is halted. If the error occurred in a write cycle, data in the internal holding register is lost.
Interrupts—If DCRn[INT] is set, the DMA drives the appropriate internal interrupt signal. The
processor can read DSRn to determine whether the transfer terminated successfully or with an
error. DSRn[DONE] is then written with a one to clear the interrupt and the DONE and error bits.
Termination
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
(MPARK).”
Freescale Semiconductor