MCF5214CVF66J Freescale Semiconductor, MCF5214CVF66J Datasheet - Page 303
MCF5214CVF66J
Manufacturer Part Number
MCF5214CVF66J
Description
IC MCU 256K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF521xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5214CVF66J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
142
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF521x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
M52210DEMO, M52211EVB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5214CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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16.4.3
BCRn, shown in
block. The offset within the memory map is based on the value of MPARK[BCR24BIT]. BCRn
decrements on the successful completion of the address transfer of a write transfer. BCRn decrements by
1, 2, 4, or 16 for byte, word, longword, or line accesses, respectively.
Figure 16-6
Figure 16-7
DSRn[DONE], shown in
When a transfer sequence is initiated and BCRn[BCR] is not a multiple of 16, 4, or 2 when the DMA is
configured for line, longword, or word transfers, respectively, DSRn[CE] is set and no transfer occurs. See
Section 16.4.5, “DMA Status Registers
16.4.4
DCRn, shown in
available only if MPARK[BCR24BIT] is set. See
more information.
Freescale Semiconductor
Address
Reset
Address
Field
R/W
Reset
Field
R/W
Byte Count Registers (BCR0–BCR3)
DMA Control Registers (DCR0–DCR3)
15
31
shows BCRn for BCR24BIT = 1.
shows BCRn for BCR24BIT = 0.
Figure
Figure 16-6
—
—
Figure 16-6. Byte Count Registers (BCRn)—BCR24BIT = 1
Figure 16-7. Byte Count Registers (BCRn)—BCR24BIT = 0
16-8, is used for configuring the DMA controller module. Note that DCRn[AT] is
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Figure
and
24 23
16-9, is set when the block transfer is complete.
Figure
IPSBAR + 0x10C, 0x14C, 0x18C, 0x1CC
IPSBAR + 0x10C, 0x14C, 0x18C, 0x1CC
(DSR0–DSR3).”
16-7, hold the number of bytes yet to be transferred for a given
0000_0000_0000_0000
Section 8.5.3, “Bus Master Park Register
0000_0000_0000_0000_0000_0000
BCR
R/W
R/W
BCR
DMA Controller Module
(MPARK)” for
0
0
16-7
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