MCF5214CVF66J Freescale Semiconductor, MCF5214CVF66J Datasheet - Page 653

• Manufacturer Part Number: MCF5214CVF66J
• Description: IC MCU 256K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF521xr

Specifications of MCF5214CVF66J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 142
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF521x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: M52210DEMO, M52211EVB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Command Sequence:
Operand Data:
Result Data:
30.5.3.3.11 Read Debug Module Register (
Read the selected debug module register and return the 32-bit result. The only valid register selection for
the
BKPT]; as well as the trigger status bits (CSR[BSTAT]) if either a level-2 breakpoint has been triggered
or a level-1 breakpoint has been triggered and no level-2 breakpoint has been enabled.
Command/Result Formats:
Table 30-20
Freescale Semiconductor
RDMREG
Command
0x01–0x1F
WCREG
DRc[4:0]
0x00
???
Result
command is CSR (DRc = 0x00). Note that this read of the CSR clears CSR[FOF, TRG, HALT,
shows the definition of DRc encoding.
15
’NOT READY’
MS ADDR
This instruction requires two longword operands. The first selects the register to
which the operand data is to be written; the second contains the data.
Successful write operations return 0xFFFF. Bus errors on the write cycle are
indicated by the setting of bit 16 in the status message and by a data pattern of
0x0001.
Debug Register Definition
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
0x2
Configuration/Status
Figure 30-37.
Table 30-20. Definition of DRc Encoding—Read
Figure 30-36.
Reserved
12
’NOT READY’
MS ADDR
11
RDMREG
WCREG
0xD
RDMREG
Command/Result Formats
Command Sequence
’NOT READY’
D[31:16]
MS DATA
8
D[15:0]
’NOT READY’
LS DATA
Mnemonic
)
7
CSR
—
100
5
REGISTER
CONTROL
WRITE
Initial State
4
0x0
—
’CMD COMPLETE’
DRc
’NOT READY’
NEXT CMD
BERR
XXX
XXX
’NOT READY’
NEXT CMD
p. 30-10
Page
Debug Support
—
0
30-35