HD6417034AFI20 Renesas Electronics America, HD6417034AFI20 Datasheet - Page 118

• Manufacturer Part Number: HD6417034AFI20
• Description: IC SUPERH MPU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417034AFI20

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 6 User Break Controller (UBC)
6.3
6.3.1
The flow from setting of break conditions to user break interrupt exception handling is described
below.
1. Break conditions are set in the break address register (BAR), break address mask register
2. The UBC checks to see if the set conditions are satisfied, using the system shown in figure 6.2.
3. On receiving the user break interrupt request, the interrupt controller checks its priority level.
4.
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(BAMR), and break bus cycle register (BBR). Set the break address in BAR, the address bits
to be masked in BAMR and the type of break bus cycle in BBR. When even one of the BBR
groups (CPU cycle/DMA cycle select bits (CD1, CD0), instruction fetch/data access select bits
(ID1, ID0), read/write select bits (RW1, RW0)) is set to 00 (no user break interrupt), there will
be no user break even when all other conditions are consistent. To use a user break interrupt,
set conditions for all three pairs.
When the break conditions are satisfied, the UBC sends a user break interrupt request to the
interrupt controller.
The user break interrupt has priority level 15, so it is accepted only if the interrupt mask level
in bits I3–I0 in the status register (SR) is 14 or lower. When the I3–I0 bit level is 15, the user
break interrupt cannot be accepted, but is held pending until user break interrupt exception
handling is carried out. NMI exception handling sets I3–I0 to level 15, so a user break cannot
occur during the NMI handling routine unless the NMI handling routine itself begins by
reducing I3–I0 to level 14 or lower. Section 5, Interrupt Controller (INTC), describes the
handling of priority levels in greater detail.
INTC sends a request signal for a user break interrupt to the CPU. When the CPU receives it,
it starts user break interrupt exception handling. Section 5.4, Interrupt Operation, describes
interrupt exception handling in more detail.
Operation
Flow of User Break Operation