HD6417034AFI20 Renesas Electronics America, HD6417034AFI20 Datasheet - Page 393

• Manufacturer Part Number: HD6417034AFI20
• Description: IC SUPERH MPU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417034AFI20

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 5—Overrun Error (ORER): Indicates that data reception ended abnormally due to an
overrun error.
Bit 5: ORER
0
1
Notes: 1. Clearing the RE bit to 0 in the serial control register does not affect the ORER bit, which
Bit 4—Framing Error (FER): FER indicates that data reception ended abnormally due to a
framing error in the asynchronous mode.
Bit 4: FER
0
1
2. RDR continues to hold the data received before the overrun error, so subsequent
retains its previous value.
receive data is lost. Serial receiving cannot continue while ORER is set to 1. In
synchronous mode, serial transmitting is disabled.
Description
Receiving is in progress or has ended normally *
ORER is cleared to 0 when:
A receive overrun error occurred *
ORER is set to 1 if reception of the next serial data ends when RDRF is set to 1
Description
Receiving is in progress or has ended normally
Clearing the RE bit to 0 in the serial control register does not affect the FER bit,
which retains its previous value.
FER is cleared to 0 when:
A receive framing error occurred. When the stop bit length is two bits, only the
first bit is checked. The second stop bit is not checked. When a framing error
occurs, the SCI transfers the receive data into RDR but does not set RDRF.
Serial receiving cannot continue while FER is set to 1. In synchronous mode,
serial transmitting is also disabled.
FER is set to 1 if the stop bit at the end of receive data is checked and found to
be 0.
The chip is reset or enters standby mode
Software reads ORER after it has been set to 1, then writes 0 in ORER
The chip is reset or enters standby mode
Software reads FER after it has been set to 1, then writes 0 in FER
Section 13 Serial Communication Interface (SCI)
2
Rev. 7.00 Jan 31, 2006 page 365 of 658
1
REJ09B0272-0700
(Initial value)
(Initial value)