HD6417034AFI20 Renesas Electronics America, HD6417034AFI20 Datasheet - Page 143

• Manufacturer Part Number: HD6417034AFI20
• Description: IC SUPERH MPU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417034AFI20

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Table 8.6
Bits 15–8:
DWW7–DWW0
0
1
Note: * Sampled in the address/data multiplexed I/O space.
8.2.4
Wait state control register 3 is a 16-bit read/write register that controls WAIT pin pull-up and the
insertion of long wait states. WCR3 is initialized to H'F800 by a power-on reset. It is not
initialized by a manual reset or in standby mode.
Bit 15—Wait Pin Pull-Up Control (WPU): WPU controls whether the WAIT pin is pulled up or
not. When cleared to 0, the pin is not pulled up; when set to 1, it is pulled up.
Bit 15: WPU
0
1
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Wait State Control Register 3 (WCR3)
Single-Mode DMA Memory Write Cycle States (External Memory Space)
WAIT
WAIT Pin Input
Signal
Not sampled
during single-mode
DMA memory write
cycle *
Sampled during
single-mode DMA
memory write cycle
(Initial value)
WAIT
WAIT
Description
WAIT pin is not pulled up
WAIT pin is pulled up
WPU
R/W
15
—
—
1
7
0
A02LW1 A02LW0 A6LW1
R/W
14
—
—
1
6
0
External Memory
Space
Areas 1, 3–5,7: 1 state, fixed
Areas 0, 2, 6: 1 state + long
wait state
Areas 1, 3–5, 7: 2 states
+ wait state from WAIT
Areas 0, 2, 6: 1 state + long
wait state + wait state from
WAIT
R/W
13
—
—
Single-Mode DMA Memory Write Cycle States
1
5
0
R/W
12
—
—
1
4
0
(External Memory Space)
Rev. 7.00 Jan 31, 2006 page 115 of 658
Section 8 Bus State Controller (BSC)
A6LW0
R/W
11
—
—
1
3
0
DRAM Space
Column address
cycle: 1 state,
fixed (short
pitch)
Column address
cycle: 2 states +
wait state from
WAIT (long
pitch)
10
—
—
—
—
0
2
0
REJ09B0272-0700
—
—
—
—
9
0
1
0
(Initial value)
Multiplexed
I/O
4 states +
wait state
from WAIT
—
—
—
—
8
0
0
0