HD6417034AFI20 Renesas Electronics America, HD6417034AFI20 Datasheet - Page 430

IC SUPERH MPU ROMLESS 112QFP

HD6417034AFI20

Manufacturer Part Number
HD6417034AFI20
Description
IC SUPERH MPU ROMLESS 112QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7030r
Datasheet

Specifications of HD6417034AFI20

Core Processor
SH-1
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
112-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

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Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417034AFI20
Manufacturer:
Renesas Electronics America
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10 000
Part Number:
HD6417034AFI20V
Manufacturer:
Renesas Electronics America
Quantity:
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Section 13 Serial Communication Interface (SCI)
Receiving Serial Data (Synchronous Mode): Figure 13.18 shows a sample flowchart for
receiving serial data. When switching from asynchronous mode to synchronous mode, make sure
that ORER, PER, and FER are cleared to 0. If PER or FER is set to 1, the RDRF bit will not be set
and both transmitting and receiving will be disabled. Figure 13.19 shows an example of SCI
receive operation.
The procedure for receiving serial data is listed below.
1. SCI initialization: select the RxD pin function with the PFC.
2. Receive error handling and break detection: if a receive error occurs, read the ORER bit in
3. SCI status check and receive data read: read the serial status register (SSR), check that RDRF
4.
Rev. 7.00 Jan 31, 2006 page 402 of 658
REJ09B0272-0700
SSR to identify the error. After executing the necessary error handling, clear ORER to 0.
Transmitting/receiving cannot resume if ORER remains set to 1.
is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0.
The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1.
To continue receiving serial data: read RDR, and clear RDRF to 0 before the frame MSB (bit
7) of the current frame is received. If the DMAC is started by a receive-data-full interrupt
(RXI) to read RDR, the RDRF bit is cleared automatically, so this step is unnecessary.

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