HD6417034AFI20 Renesas Electronics America, HD6417034AFI20 Datasheet - Page 46

• Manufacturer Part Number: HD6417034AFI20
• Description: IC SUPERH MPU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417034AFI20

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 2 CPU
2.1.2
Control registers consist of the 32-bit status register (SR), global base register (GBR), and vector
base register (VBR). The status register indicates processing states. The global base register
functions as a base address for the indirect GBR addressing mode to transfer data to the registers
of on-chip supporting modules. The vector base register functions as the base address of the
exception vector area including interrupts.
Rev. 7.00 Jan 31, 2006 page 18 of 658
REJ09B0272-0700
SR
31
31
31
Control Registers
M Q I3 I2 I1 I0
9 8 7 6 5 4 3 2 1 0
GBR
VBR
Figure 2.2 Control Registers
S T
0
0
SR: Status register
T bit: The MOVT, CMP, TAS, TST,
S bit: Used by the MAC instruction.
Reserved bits. These bits always read 0.
The write value should always be 0.
Bits I3–I0: Interrupt mask bits.
M and Q bits: Used by the DIV0U, DIV0S,
Global base register (GBR):
Indicates the base address in indirect
GBR addressing mode. The indirect GBR
addressing mode is used to transfer data
to the on-chip supporting module register
area, etc.
Vector base register (VBR):
Stores the base address of the exception
vector area.
BT, BF, SETT, and CLRT instructions
use the T bit to indicate true (1) or
false (0). The ADDV, ADDC, SUBV,
SUBC, DIV0U, DIV0S, DIV1, NEGC,
SHAR, SHAL, SHLR, SHLL, ROTR,
ROTL, ROTCR and ROTCL
instructions also use the T bit to indicate
carry/borrow or overflow/underflow
and DIV1 instructions.