HD6417034AFI20 Renesas Electronics America, HD6417034AFI20 Datasheet - Page 76

• Manufacturer Part Number: HD6417034AFI20
• Description: IC SUPERH MPU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417034AFI20

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 2 CPU
2.5.2
In addition to the ordinary program execution states, the CPU also has a power-down state in
which CPU operation halts and power consumption is reduced There are two power-down state
modes: sleep mode and standby mode.
Sleep Mode: When the standby bit SBY (in the standby control register, SBYCR) is cleared to 0
and a SLEEP instruction is executed, the CPU switches from program execution state to sleep
mode. In sleep mode, the CPU halts and the contents of its internal registers and the data in on-
chip RAM are stored. The on-chip supporting modules other than the CPU do not halt in sleep
mode.
Sleep mode is cleared by a reset, any interrupt, or a DMA address error; the CPU returns to
ordinary program execution state through the exception handling state.
Software Standby Mode: To enter standby mode, set standby bit SBY (in the standby control
register, SBYCR) to 1 and execute a SLEEP instruction. In standby mode, all CPU, on-chip
supporting module and oscillator functions are halted. CPU internal register contents and on-chip
RAM data are held.
Standby mode is cleared by a reset or an external NMI interrupt. For resets, the CPU returns to the
ordinary program execution state through the exception handling state when placed in a reset state
during the oscillator settling time. For NMI interrupts, the CPU returns to the ordinary program
execution state through the exception handling state after the oscillator settling time has elapsed.
In this mode, power consumption drops markedly, since the oscillator stops.
Table 2.19 Power-Down State
Note: * Differs depending on the supporting module and pin.
Rev. 7.00 Jan 31, 2006 page 48 of 658
REJ09B0272-0700
Mode
Sleep
mode
Standby
mode
Power-Down State
Conditions
Execute SLEEP
instruction with
SBY bit cleared
to 0 in SBYCR
Execute SLEEP
instruction with
SBY bit set to 1
in SBYCR
Clock CPU
Run
Halted Halted Halted and
Halted Run
On-Chip
Supporting
Modules
initialized *
State
CPU
Regi-
sters RAM
Held
Held
Held
Held
I/O
Ports
Held
Held or
high-Z *
(select-
able)
Canceling
1. Interrupt
2. DMA address
3. Power-on
4. Manual reset
1. NMI
2. Power-on
3. Manual reset
error
reset
reset