HD6417034AFI20 Renesas Electronics America, HD6417034AFI20 Datasheet - Page 153

• Manufacturer Part Number: HD6417034AFI20
• Description: IC SUPERH MPU ROMLESS 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7030r

Specifications of HD6417034AFI20

• Core Processor: SH-1
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Bit 14—Parity Output Force (PFRC): PFRC selects whether to produce a forced parity output
for testing the parity error check function. When cleared to 0, there is no forced output; when set
to 1, it produces a forced high-level output from the DPH and DPL pins when data is output,
regardless of the parity.
Bit 14: PFRC
0
1
Bit 13—Parity Polarity (PEO): PEO selects even or odd parity. When cleared to 0, parity is
even; when set to 1, parity is odd.
Bit 13: PEO
0
1
Bits 12 and 11—Parity Check Enable Bits 1 and 0 (PCHK1 and PCHK0): These bits
determine whether or not parity is checked and generated, and select the check and generation
spaces.
Bit 12:
PCHK1
0
1
Bits 10–0—Reserved: These bits are always read as 0. The write value should always be 0.
Bit 11:
PCHK0
0
1
0
1
Description
Parity output not forced
High output forced
Description
Even parity
Odd parity
Description
Parity not checked and not generated
Parity checked and generated only in DRAM area
Parity checked and generated in DRAM area and area 2
Reserved
Rev. 7.00 Jan 31, 2006 page 125 of 658
Section 8 Bus State Controller (BSC)
REJ09B0272-0700
(Initial value)
(Initial value)
(Initial value)