DF2367VTE33 Renesas Electronics America, DF2367VTE33 Datasheet - Page 211

• Manufacturer Part Number: DF2367VTE33
• Description: IC H8S MCU FLASH 384K 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2300r

Specifications of DF2367VTE33

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: I²C, IrDA, SCI, SmartCard
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: HD64F2367VTE33; HD64F2367VTE33

16-Bit Access Space: Figure 6.8 illustrates data alignment control for the 16-bit access space.
With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are
used for accesses. The amount of data that can be accessed at one time is one byte or one word,
and a longword access is executed as two word accesses.
In byte access, whether the upper or lower data bus is used is determined by whether the address is
even or odd. The upper data bus is used for an even address, and the lower data bus for an odd
address.
Figure 6.8 Access Sizes and Data Alignment Control (16-bit Access Space)
Figure 6.7 Access Sizes and Data Alignment Control (8-Bit Access Space)
Byte size
Word size
Longword
size
Byte size
Byte size
Word size
Longword
size
• Even address
• Odd address
1st bus cycle
2nd bus cycle
1st bus cycle
2nd bus cycle
3rd bus cycle
4th bus cycle
1st bus cycle
2nd bus cycle
D15
D15
Upper data bus
Upper data bus
Rev.6.00 Mar. 18, 2009 Page 151 of 980
D8 D7
D8 D7
Section 6 Bus Controller (BSC)
Lower data bus
Lower data bus
REJ09B0050-0600
D0
D0