DF2367VTE33 Renesas Electronics America, DF2367VTE33 Datasheet - Page 697
DF2367VTE33
Manufacturer Part Number
DF2367VTE33
Description
IC H8S MCU FLASH 384K 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2300r
Specifications of DF2367VTE33
Core Processor
H8S/2000
Core Size
16-Bit
Speed
33MHz
Connectivity
I²C, IrDA, SCI, SmartCard
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
84
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Other names
HD64F2367VTE33
HD64F2367VTE33
HD64F2367VTE33
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2367VTE33V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Bit Bit Name
2
1
0
15.3.4
ICIER is an 8-bit readable/writable register that enables or disables interrupt sources and
acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits to be
received.
Bit Bit Name
7
6
BC2
BC1
BC0
TIE
TEIE
I
2
C Bus Interrupt Enable Register (ICIER)
Initial Value R/W
0
0
0
Initial Value R/W
0
0
R/W
R/W
R/W
R/W
R/W
Description
Bit Counter 2 to 0
These bits specify the number of bits to be transferred next.
When read, the remaining number of transfer bits is
indicated. The data is transferred with one addition
acknowledge bit. Bit BC2 to BC0 settings should be made
during an interval between transfer frames. If bits BC2 to
BC0 are set to a value other than 000, the setting should be
made while the SCL line is low. The value returns to 000 at
the end of a data transfer, including the acknowledge bit.
With the clock synchronous serial format, these bits should
not be modified.
000: 9
001: 2
010: 3
011: 4
100: 5
101: 6
110: 7
111: 8
Description
Transmit Interrupt Enable
When the TDRE bit in ICSR is set to 1, this bit enables or
disables the transmit data empty interrupt (TXI).
0: Transmit data empty interrupt request (TXI) is disabled.
1: Transmit data empty interrupt request (TXI) is enabled.
Transmit End Interrupt Enable
This bit enables or disables the transmit end interrupt (TEI)
at the rising of the ninth clock while the TDRE bit in ICSR is
1. TEI can be canceled by clearing the TEND bit or the
TEIE bit to 0.
0: Transmit end interrupt request (TEI) is disabled.
1: Transmit end interrupt request (TEI) is enabled.
Section 15 I
Rev.6.00 Mar. 18, 2009 Page 637 of 980
2
C Bus Interface2 (IIC2) (Option)
REJ09B0050-0600
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