DF2505FC26V Renesas Electronics America, DF2505FC26V Datasheet - Page 460
DF2505FC26V
Manufacturer Part Number
DF2505FC26V
Description
IC H8S/2505 MCU FLASH 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2500r
Specifications of DF2505FC26V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
26MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
104
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 13 Serial Communication Interface (SCI)
Notes: 1. Only a 0 can be written to this bit to clear the flag.
Rev. 6.00 Sep. 24, 2009 Page 412 of 928
REJ09B0099-0600
Bit
3
2
1
0
2. This bit is cleared by DTC only when DISEL is 0 with the transfer counter other than 0.
3. To clear the flag by using the CPU, write 0 to the flag and then read it once again.
Bit Name
PER
TEND
MPB
MPBT
Initial
Value
0
1
0
0
R/W
R/(W)*
R
R
R/W
1
Description
Parity Error
Indicates that a parity error occurred during reception
using parity addition in asynchronous mode, causing
abnormal termination.
[Setting condition]
•
If a parity error occurs, the receive data is transferred to
RDR but the RDRF flag is not set. Also, subsequent
serial reception cannot be continued while the PER flag
is set to 1. In clocked synchronous mode, serial
transmission cannot be continued, either.
[Clearing condition]
•
The PER flag is not affected and retains its previous state
when the RE bit in SCR is cleared to 0.
Transmit End
Indicates that transmission has been ended.
[Setting conditions]
•
•
[Clearing conditions]
•
•
Multiprocessor Bit
MPB stores the multiprocessor bit in the receive data.
When the RE bit in SCR is cleared to 0 its previous state
is retained.
Multiprocessor Bit Transfer
MPBT stores the multiprocessor bit to be added to the
transmit data.
When a parity error is detected during reception
When 0 is written to PER after reading PER = 1*
When the TE bit in SCR is 0
When TDRE = 1 at transmission of the last bit of a 1-
byte serial transmit character
When 0 is written to TDRE after reading TDRE = 1
When the DTC*
request and transfers transmit data to TDR
2
is activated by a TXI interrupt
3
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