DF2505FC26V Renesas Electronics America, DF2505FC26V Datasheet - Page 466
DF2505FC26V
Manufacturer Part Number
DF2505FC26V
Description
IC H8S/2505 MCU FLASH 144QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2500r
Specifications of DF2505FC26V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
26MHz
Connectivity
I²C, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
104
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Section 13 Serial Communication Interface (SCI)
13.3.9
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 13.2 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode,
clocked synchronous mode, and Smart Card interface mode. The initial value of BRR is H'FF, and
it can be read or written to by the CPU at all times.
Table 13.2 Relationships between N Setting in BRR and Bit Rate B
Legend:
B:
N:
φ:
n and S: Determined by the SMR settings shown in the following tables.
Table 13.3 shows sample N settings in BRR in normal asynchronous mode. Table 13.4 shows the
maximum bit rate for each frequency in normal asynchronous mode. Table 13.6 shows sample N
settings in BRR in clocked synchronous mode. Table 13.8 shows sample N settings in BRR in
Smart Card interface mode. In Smart Card interface mode, S (the number of basic clock periods in
a 1-bit transfer interval) can be selected. For details, see section 13.7.4, Receive Data Sampling
Timing and Reception Margin. Tables 13.5 and 13.7 show the maximum bit rates with external
clock input.
Rev. 6.00 Sep. 24, 2009 Page 418 of 928
REJ09B0099-0600
Communication Mode
Asynchronous Mode
Clocked Synchronous
Mode
Smart Card Interface
Mode
CKS1
0
0
1
1
SMR Setting
Bit Rate Register (BRR)
Bit rate (bit/s)
BRR setting for baud rate generator (0 ≤ N ≤ 255)
Operating frequency (MHz)
CKS0
0
1
0
1
Clock
Source
φ
φ/4
φ/16
φ/64
Bit Rate
B =
B =
B =
64
S
8
n
0
1
2
3
2
2
2
2n+1
2n-1
2n-1
10
10
10
(N + 1)
(N + 1)
6
6
6
(N + 1)
Error
Error (%) = {
Error (%) = {
BCP1
0
0
1
1
SMR Setting
B
B
BCP0
0
1
0
1
64
S
2
2
⎯
2n+1
2n-1
10
10
6
6
S
32
64
372
256
(N + 1)
(N + 1)
-1 }
-1 }
100
100
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