DF2505FC26V Renesas Electronics America, DF2505FC26V Datasheet - Page 690

• Manufacturer Part Number: DF2505FC26V
• Description: IC H8S/2505 MCU FLASH 144QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2500r

Specifications of DF2505FC26V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 26MHz
• Connectivity: I²C, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 104
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 18 Controller Area Network (HCAN) [H8S/2556 Group]
Table 18.3 Setting Range for TSEG1 and TSEG2 in BCR
Note:
Mailbox Transmit/Receive Settings: The HCAN has 16 mailboxes. Mailbox 0 is receive-only,
while mailboxes 1 to 15 can be set for transmission or reception. The Initial status of mailboxes 1
to 15 is for transmission. Mailbox transmit/receive settings are not initialized by a software reset.
Clearing a bit to 0 in the mailbox configuration register (MBCR) designates the corresponding
mailbox for transmission use, whereas a setting of 1 in MBCR designates the corresponding
mailbox for reception use. When setting mailboxes for reception, in order to improve message
reception efficiency, high-priority messages should be set in low-to-high mailbox order.
Mailbox (Message Control/Data) Initial Settings: Message control/data are held in RAM, and
so their initial values are undefined after power is supplied. Initial values must therefore be set in
all the mailboxes (by writing 0s or 1s).
Setting the Message Transmission Method: The following two kinds of message transmission
methods are available.
Rev. 6.00 Sep. 24, 2009 Page 642 of 928
REJ09B0099-0600
(BCR[11:8])
TSEG1
The time quantum value for TSEG1 and TSEG2 is the TSEG value + 1.
*
When baud rate prescaler (BRP), BCR[13:8], is not B'000000 (2 × system clock), this
can be set.
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Yes*
Yes*
Yes*
Yes*
Yes*
Yes*
Yes*
Yes*
Yes*
Yes*
Yes*
Yes*
001
No
2
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
010
3
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
011
No
4
TSEG2 (BCR[14:12])
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
100
No
No
5
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
101
No
No
No
6
110
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
7
111
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
8