UPD78F9221CS-CAC-A Renesas Electronics America, UPD78F9221CS-CAC-A Datasheet - Page 171

• Manufacturer Part Number: UPD78F9221CS-CAC-A
• Description: MCU 8BIT 2KB FLASH 20PIN
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9221CS-CAC-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) Analog input channel specification register (ADS)
(3) 10-bit A/D conversion result register (ADCR)
Symbol
Cautions 2. If a bit other than ADCS of ADM is manipulated while A/D conversion is stopped (ADCS = 0)
ADCR
This register specifies the input port of the analog voltage to be A/D converted.
ADS can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Caution Be sure to clear bits 2 to 7 of ADS to 0.
This register is a 16-bit register that stores the A/D conversion result. The higher six bits are fixed to 0. Each
time A/D conversion ends, the conversion result is loaded from the successive approximation register, and is
stored in ADCR in order starting from bit 1 of FF19H. FF19H indicates the higher 2 bits of the conversion result,
and FF18H indicates the lower 8 bits of the conversion result.
ADCR can be read by a 16-bit memory manipulation instruction.
Reset signal generation makes ADCR undefined.
Caution When writing to the A/D converter mode register (ADM) and analog input channel specification
Address: FF18H, FF19H
0
3. A/D conversion must be stopped (ADCS = 0) before rewriting bits FR0 to FR2.
4. Be sure to clear bits 6, 2, and 1 to 0.
register (ADS), the contents of ADCR may become undefined. Read the conversion result
following conversion completion before writing to ADM and ADS. Using timing other than the
above may cause an incorrect conversion result to be read.
and then A/D conversion is started, execute two NOP instructions or an instruction
equivalent to two machine cycles, and set ADCS to 1.
Figure 10-5. Format of Analog Input Channel Specification Register (ADS)
0
Symbol
Address: FF81H
Figure 10-6. Format of 10-bit A/D Conversion Result Register (ADCR)
ADS
0
ADS1
0
7
0
0
1
1
0
FF19H
After reset: Undefined
After reset: 00H
ADS0
0
0
6
0
1
0
1
CHAPTER 10 A/D CONVERTER
User’s Manual U16898EJ6V0UD
0
ANI0
ANI1
ANI2
ANI3
5
0
R/W
Analog input channel specification
0
4
R
0
3
0
2
ADS1
1
FF18H
ADS0
0
169