UPD78F9221CS-CAC-A Renesas Electronics America, UPD78F9221CS-CAC-A Datasheet - Page 191

• Manufacturer Part Number: UPD78F9221CS-CAC-A
• Description: MCU 8BIT 2KB FLASH 20PIN
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9221CS-CAC-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.3 Registers Controlling Serial Interface UART6
(1) Asynchronous serial interface operation mode register 6 (ASIM6)
Address: FF90H After reset: 01H R/W
Serial interface UART6 is controlled by the following nine registers.
Notes 1.
Symbol
ASIM6
This 8-bit register controls the serial communication operations of serial interface UART6.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 01H.
Remark ASIM6 can be refreshed (the same value is written) by software during a communication operation
Asynchronous serial interface operation mode register 6 (ASIM6)
Asynchronous serial interface reception error status register 6 (ASIS6)
Asynchronous serial interface transmission status register 6 (ASIF6)
Clock selection register 6 (CKSR6)
Baud rate generator control register 6 (BRGC6)
Asynchronous serial interface control register 6 (ASICL6)
Input switch control register (ISC)
Port mode register 4 (PM4)
Port register 4 (P4)
Figure 11-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (1/2)
2.
3.
(when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 = 1 or bit 7 (POWER6) and bit 5 (RXE6) of ASIM6
= 1).
POWER6
The output of the T
POWER6 is cleared to 0 during a transmission.
Asynchronous serial interface reception error status register 6 (ASIS6), asynchronous serial interface
transmission status register 6 (ASIF6), bit 7 (SBRF6) and bit 6 (SBRT6) of asynchronous serial
interface control register 6 (ASICL6), and receive buffer register 6 (RXB6) are reset.
A base clock (f
one clock of the base clock (f
POWER6
0
1
<7>
Note 1
Note 3
Disable operation of the internal operation clock (fixes the clock to low level) and asynchronously
resets the internal circuit
Enable operation of the internal operation clock
TXE6
XCLK6
<6>
X
) is supplied as the internal operation clock when the POWER6 bit is set to 1 and
D6 pin goes high and the input from the R
CHAPTER 11 SERIAL INTERFACE UART6
RXE6
<5>
XCLK6
User’s Manual U16898EJ6V0UD
Enabling/disabling operation of internal operation clock
Note 2
) has elapsed.
.
PS61
4
PS60
3
X
D6 pin is fixed to the high level when
CL6
2
SL6
1
ISRM6
0
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