UPD78F9221CS-CAC-A Renesas Electronics America, UPD78F9221CS-CAC-A Datasheet - Page 255
UPD78F9221CS-CAC-A
Manufacturer Part Number
UPD78F9221CS-CAC-A
Description
MCU 8BIT 2KB FLASH 20PIN
Manufacturer
Renesas Electronics America
Series
78K0S/Kx1+r
Datasheet
1.UPD78F9221MC-5A4-A.pdf
(418 pages)
Specifications of UPD78F9221CS-CAC-A
Core Processor
78K0S
Core Size
8-Bit
Speed
10MHz
Connectivity
LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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15.4 Cautions for Power-on-Clear Circuit
voltage (V
release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
<Action>
software counter that uses a timer, and then initialize the ports.
Note 1
If supply voltage fluctuation is 50 ms or less in vicinity of POC detection voltage
In a system where the supply voltage (V
After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of a
Notes 1.
POC
2.
), the system may be repeatedly reset and released from the reset status. In this case, the time from
No
If reset is generated again during this period, initialization processing <2> is not started.
A flowchart is shown on the next page.
Figure 15-3. Example of Software Processing After Release of Reset (1/2)
Setting 8-bit timer H1
(50 ms
50 ms has passed?
processing <1>
processing <2>
(TMIFH1 = 1?)
Initialization
Clears WDT
Initialization
Reset
is measured)
Yes
Power-on-clear
CHAPTER 15 POWER-ON-CLEAR CIRCUIT
DD
User’s Manual U16898EJ6V0UD
) fluctuates for a certain period in the vicinity of the POC detection
; Check reset source
; Setting
; f
Initialization of ports
Setting WDT
timer, A/D converter, etc.
Source: f
Timer starts (TMHE1 = 1)
XP
= High-speed internal oscillation clock (8.4 MHz (MAX.))/2
the division ratio of the system clock,
51 ms when the compare value is 25
XP
(2.1 MHz (MAX.))/2
Note 2
12
,
2
(default value)
253
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