UPD78F9221CS-CAC-A Renesas Electronics America, UPD78F9221CS-CAC-A Datasheet - Page 180

no-image

UPD78F9221CS-CAC-A

Manufacturer Part Number
UPD78F9221CS-CAC-A
Description
MCU 8BIT 2KB FLASH 20PIN
Manufacturer
Renesas Electronics America
Series
78K0S/Kx1+r
Datasheet

Specifications of UPD78F9221CS-CAC-A

Core Processor
78K0S
Core Size
8-Bit
Speed
10MHz
Connectivity
LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
15
Program Memory Size
2KB (2K x 8)
Program Memory Type
FLASH
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
10.6 Cautions for A/D Converter
(1) Operating current in STOP mode
(2) Input range of ANI0 to ANI3
(3) Conflicting operations
178
To satisfy the DC characteristics of the supply current in the STOP mode, clear bit 7 (ADCS) and bit 0 (ADCE) of
the A/D converter mode register (ADM) to 0 before executing the STOP instruction.
Observe the rated range of the ANI0 to ANI3 input voltage. If a voltage of AV
in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel
becomes undefined. In addition, the converted values of the other channels may also be affected.
<1> Conflict between A/D conversion result register (ADCR, ADCRH) write and ADCR, ADCRH read by
<2> Conflict between ADCR, ADCRH write and A/D converter mode register (ADM) write or analog input
instruction upon the end of conversion
ADCR, ADCRH read has priority. After the read operation, the new conversion result is written to ADCR,
ADCRH.
channel specification register (ADS) write upon the end of conversion
ADM or ADS write has priority. ADCR, ADCRH write is not performed, nor is the conversion end interrupt
signal (INTAD) generated.
CHAPTER 10 A/D CONVERTER
User’s Manual U16898EJ6V0UD
REF
or higher and V
SS
or lower (even

Related parts for UPD78F9221CS-CAC-A