UPD78F9221CS-CAC-A Renesas Electronics America, UPD78F9221CS-CAC-A Datasheet - Page 340

• Manufacturer Part Number: UPD78F9221CS-CAC-A
• Description: MCU 8BIT 2KB FLASH 20PIN
• Manufacturer: Renesas Electronics America
• Series: 78K0S/Kx1+r

Specifications of UPD78F9221CS-CAC-A

• Core Processor: 78K0S
• Core Size: 8-Bit
• Speed: 10MHz
• Connectivity: LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

338
CALL
CALLT
RET
RETI
PUSH
POP
MOVW
BR
BC
BNC
BZ
BNZ
BT
BF
DBNZ
NOP
EI
DI
HALT
STOP
Mnemonic
Remark
!addr16
[addr5]
PSW
rp
PSW
rp
SP, AX
AX, SP
!addr16
$addr16
AX
$saddr16
$saddr16
$saddr16
$saddr16
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
B, $addr16
C, $addr16
saddr, $addr16
One instruction clock cycle is one CPU clock cycle (f
register (PCC).
Operand
CHAPTER 20 INSTRUCTION SET OVERVIEW
Bytes
3
1
1
1
1
1
1
1
2
2
3
2
1
2
2
2
2
4
4
3
4
4
4
3
4
2
2
3
1
3
3
1
1
User’s Manual U16898EJ6V0UD
Clocks
10
10
10
10
10
10
6
8
6
8
2
4
4
6
8
6
6
6
6
6
6
6
6
8
8
6
6
8
2
6
6
2
2
(saddr)
(SP
PC
(SP
PC
PC
PC
PC
SP
(SP
(SP
PSW
rp
SP
AX
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
B
C
PC
No Operation
IE
IE
Set HALT Mode
Set STOP Mode
H
H
L
H
H
H
B
C
1 (Enable Interrupt)
0 (Disable Interrupt)
1)
1)
1)
1)
SP + 3
(SP + 1), rp
AX
SP
addr16, SP
addr16
PC + 2 + jdisp8
PC + 2 + jdisp8 if CY = 1
PC + 2 + jdisp8 if CY = 0
PC + 2 + jdisp8 if Z = 1
PC + 2 + jdisp8 if Z = 0
PC + 4 + jdisp8 if (saddr.bit) = 1
PC + 4 + jdisp8 if sfr.bit = 1
PC + 3 + jdisp8 if A.bit = 1
PC + 4 + jdisp8 if PSW.bit = 1
PC + 4 + jdisp8 if (saddr.bit) = 0
PC + 4 + jdisp8 if sfr.bit = 0
PC + 3 + jdisp8 if A.bit = 0
PC + 4 + jdisp8 if PSW.bit = 0
PC + 3 + jdisp8 if (saddr)
(00000000, addr5), SP
(00000000, addr5 + 1),
(SP + 1), PC
(SP + 1), PC
A, PC
(SP), SP
1, then PC
1, then PC
(saddr)
(PC + 3)
(PC + 1)
PSW, SP
rp
L
H
CPU
, (SP
X
) selected by the processor clock control
L
H
H
L
L
1, then
Operation
SP + 1
, (SP
, (SP
SP
2)
(SP), SP
PC + 2 + jdisp8 if B
PC + 2 + jdisp8 if C
(SP), SP
(SP), PSW
SP
2
rp
2)
2)
L
1
, SP
SP
0
(PC + 3)
(PC + 1)
SP + 2
SP + 2
SP
(SP + 2),
2
L
L
,
,
2
0
0
Z
R
R
Flag
AC CY
R
R
R
R