UPD78F0513AGB-GAF-AX Renesas Electronics America, UPD78F0513AGB-GAF-AX Datasheet - Page 518
UPD78F0513AGB-GAF-AX
Manufacturer Part Number
UPD78F0513AGB-GAF-AX
Description
MCU 8BIT 44-LQFP
Manufacturer
Renesas Electronics America
Series
78K0/Kx2r
Datasheet
1.UPD78F0500MC-5A4-A.pdf
(982 pages)
Specifications of UPD78F0513AGB-GAF-AX
Core Processor
78K/0
Core Size
8-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F0513AGB-GAF-AX
Manufacturer:
SEMIKRON
Quantity:
21
Company:
Part Number:
UPD78F0513AGB-GAF-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Notes 1.
Caution During transfer (TSF0 = 1), rewriting serial operation mode specification register 0 (CSIMA0), serial
BUSYLV0
ERRE0
2.
BUSYE0
ERRF0
TSF0
status register 0 (CSIS0), divisor selection register 0 (BRGCA0), automatic data transfer address
point specification register 0 (ADTP0), automatic data transfer interval specification register 0
(ADTI0), and serial I/O shift register 0 (SIOA0) are prohibited. However, these registers can be read
and re-written to the same value. In addition, the buffer RAM can be rewritten during transfer.
In bit error detection by busy input, the active level specified by BUSYLV0 is detected.
The ERRE0 setting is valid even when BUSYE0 = 0.
0
1
0
1
0
1
0
1
0
1
Note 2
Note 1
Busy signal detection disabled (input via BUSY0 pin is ignored)
Busy signal detection enabled and communication wait by busy signal is executed
Low level
High level
Error detection disabled
Error detection enabled
Bit error detected (when ERRE0 = 1, the level specified by BUSYLV0 during the data bit transfer
period is detected via BUSY0 pin input).
From the transfer start to the end of the specified transfer
Bit 7 (CSIAE0) of serial operation mode specification register 0 (CSIMA0) = 0
At reset input
When communication is started by setting bit 0 (ATSTA0) of serial trigger register 0 (CSIT0) to 1
or writing to SIOA0.
Bit 7 (CSIAE0) of serial operation mode specification register 0 (CSIMA0) = 0
At reset input
At the end of the specified transfer
When transfer is stopped by setting bit 1 (ATSTP0) of serial trigger register 0 (CSIT0) to 1
Figure 17-3. Format of Serial Status Register 0 (CSIS0) (2/2)
Busy signal detection enable/disable
Bit error detection enable/disable
Busy signal active level setting
Transfer status detection flag
Bit error detection flag
CHAPTER 17 SERIAL INTERFACE CSIA0
518
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