UPD78F0513AGB-GAF-AX Renesas Electronics America, UPD78F0513AGB-GAF-AX Datasheet - Page 624

• Manufacturer Part Number: UPD78F0513AGB-GAF-AX
• Description: MCU 8BIT 44-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0513AGB-GAF-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
(3) Multiplication/division data register B0 (MDB0)
Cautions 1. Do not change the value of MDB0 during operation processing (while bit 7 (DMUE) of
Address: FF66H, FF67H
Symbol
MDB0
The functions of MDA0 when an operation is executed are shown in the table below.
Remark
The register configuration differs between when multiplication is executed and when division is executed, as
follows.
• Register configuration during multiplication
• Register configuration during division
MDA0 fetches the calculation result as soon as the clock is input, when bit 7 (DMUE) of multiplier/divider control
register 0 (DMUC0) is set to 1.
MDA0H and MDA0L can be set by an 8-bit or 16-bit memory manipulation instruction.
Reset signal generation clears MDA0H and MDA0L to 0000H.
MDB0 is a register that stores a 16-bit multiplier B in the multiplication mode and a 16-bit divisor in the division
mode.
MDB0 can be set by an 8-bit or 16-bit memory manipulation instruction.
Reset signal generation clears MDB0 to 0000H.
MDA0 (bits 15 to 0) × MDB0 (bits 15 to 0) = MDA0 (bits 31 to 0)
MDA0 (bits 31 to 0) ÷ MDB0 (bits 15 to 0) = MDA0 (bits 31 to 0) … SDR0 (bits 15 to 0)
DMUSEL0
<Multiplier A>
<Dividend>
2. Do not clear MDB0 to 0000H in the division mode. If set, undefined operation results are stored
MDB
015
0
1
multiplier/divider control register 0 (DMUC0) is 1). Even in this case, the operation is executed,
but the result is undefined.
in MDA0 and SDR0.
DMUSEL0: Bit 0 of multiplier/divider control register 0 (DMUC0)
MDB
014
Figure 19-4. Format of Multiplication/Division Data Register B0 (MDB0)
MDB
013
Table 19-2. Functions of MDA0 During Operation Execution
After reset: 0000H
Division mode
Multiplication mode
FF67H (MDB0H)
MDB
012
<Multiplier B>
<Divisor>
Operation Mode
MDB
011
MDB
010
R/W
MDB
009
<Product>
<Quotient>
MDB
008
Dividend
Higher 16 bits: 0, Lower
16 bits: Multiplier A
MDB
007
Setting
MDB
006
<Remainder>
CHAPTER 19 MULTIPLIER/DIVIDER
MDB
005
FF66H (MDB0L)
MDB
004
Division result (quotient)
Multiplication result
(product)
MDB
003
Operation Result
MDB
002
MDB
001
MDB
000
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