UPD70F3744GJ-GAE-AX Renesas Electronics America, UPD70F3744GJ-GAE-AX Datasheet - Page 882

• Manufacturer Part Number: UPD70F3744GJ-GAE-AX
• Description: MCU 32BIT V850ES/JX3 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3r

Specifications of UPD70F3744GJ-GAE-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 32MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 128
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JJ3
R01UH0016EJ0400 Rev.4.00
Sep 30, 2010
16-bit
interval
timer M
(TMM)
Watch
timer
functions
Watchdog
timer 2
function
Function
TM0CMP0,
TM0CTL0
registers
PRSM0 register
PRSCM0
register
WTM register
Cautions
Default-start
watchdog timer
WDTM2 register
Details of
Function
Rewriting the TM0CMP0 and TM0CTL0 registers is prohibited while TMM0 is
operating.
If these registers are rewritten while the TM0CE bit is 1, the operation cannot be
guaranteed.
If they are rewritten by mistake, clear the TM0CTL0.TM0CE bit to 0, and re-set
the registers.
Do not change the values of the BGCS00 and BGCS01 bits during watch timer
operation.
Set the PRSM0 register before setting the BGCE0 bit to 1.
Set the PRSM0 and PRSCM0 registers according to the main clock frequency
that is used so as to obtain an f
Do not rewrite the PRSCM0 register during watch timer operation.
Set the PRSCM0 register before setting the PRSM0.BGCE0 bit to 1.
Set the PRSM0 and PRSCM0 registers according to the main clock frequency
that is used so as to obtain an f
Rewrite the WTM2 to WTM7 bits while both the WTM0 and WTM1 bits are 0.
Some time is required before the first watch timer interrupt request signal
(INTWT) is generated after operation is enabled (WTM.WTM1 and WTM.WTM0
bits = 1).
It takes 0.515625 seconds (max.) for the first INTWT signal to be generated (2
1/32768 = 0.015625 seconds longer (max.)).
The INTWT signal is then generated every 0.5 seconds.
Watchdog timer 2 automatically starts in the reset mode following reset release.
When watchdog timer 2 is not used, either stop its operation before reset is
executed via this function, or clear watchdog timer 2 once and stop it within the
next interval time.
Also, write to the WDTM2 register for verification purposes only once, even if the
default settings (reset mode, interval time: f
For the non-maskable interrupt servicing due to a non-maskable interrupt request
signal (INTWDT2), see 19.2.2 (2) From INTWDT2 signal.
Accessing the WDTM2 register is prohibited in the following statuses. For details,
see 3.4.8 (2) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates with the subclock and the main clock oscillation is
• When the CPU operates with the internal oscillation clock
For details of the WDCS20 to WDCS24 bits, see Table 11-2 Watchdog Timer 2
Clock Selection.
Although watchdog timer 2 can be stopped just by stopping the operation of the
internal oscillator, clear the WDTM2 register to 00H to securely stop the timer (to
avoid selection of the main clock or subclock due to an erroneous write
operation).
If the WDTM2 register is rewritten twice after reset, an overflow signal is forcibly
generated and the counter is reset.
To intentionally generate an overflow signal, write data to the WDTM2 register
only twice, or write a value other than “ACH” to the WDTE register only once.
However, when watchdog timer 2 is set to stop operation, an overflow signal is
not generated even if data is written to the WDTM2 register only twice, or a value
other than “ACH” is written to the WDTE register only once.
stopped
BRG
BRG
frequency of 32.768 kHz.
frequency of 32.768 kHz.
Cautions
R
/2
19
) do not need to be changed.
APPENDIX E LIST OF CAUTIONS
9
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