UPD70F3768GF-GAT-AX Renesas Electronics America, UPD70F3768GF-GAT-AX Datasheet - Page 1120

• Manufacturer Part Number: UPD70F3768GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-U 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Ur

Specifications of UPD70F3768GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
(3) HcCommandStatus register (Offset 08H)
31 to 18
17, 16
15 to 4
3
2
1
Bit position
After reset: 0000 0000H
SOC[1:0]
OCR
BLF
CLF
Bit name
−
−
Reserved. (Be sure to write “0” to these bits.)
Scheduling Overrun Count
Counts the schedule overrun count. Counts up each time a schedule overrun occurs.
Counting up continues even if the SO bit of the HcInterruptStatus register is set to “1”.
These bits are read-only.
Reserved. (Be sure to write “0” to these bits.)
Ownership Change Request
Requests to change the control right of the OHCI host controller.
Bulk List Filled
Indicates whether a TD exists in a bulk list.
This bit is always set to “1” by the host controller driver (HCD) when a TD is added to the
ED of a bulk list.
The OHCI host controller checks this bit when starting bulk list head processing.
List head processing is not started if a TD exists while this bit is set to “0”. If this bit is set to
“1”, the OHCI host controller sets it to “0” and control ED processing starts. If a TD is
detected in a bulk list, this bit is set to “1” again to continue bulk TD processing.
The driver must set this bit before reconfiguring the list, setting the BLE bit of the
HcCommand register, and starting list processing.
Control List Filled
Indicates whether a control list exists.
This bit is always set to “1” by the host controller driver (HCD) when a TD is added to the
ED of a control list.
The OHCI host controller checks this bit when starting control list head processing.
List head processing is not started while this bit is set to “0”. If this bit is set to “1”, the OHCI
host controller sets it to “0” and control list processing starts. If a TD is detected in a control
list, this bit is set to “1” again to continue control list processing.
The driver must set this bit before reconfiguring the list, setting the CLE bit of the
HcCommand register, and starting list processing.
31
15
23
0
0
0
7
0
R/W
30
22
14
0
0
0
6
0
29
21
13
5
0
0
0
0
28
12
20
0
0
0
4
0
CHAPTER 21 USB HOST CONTROLLER (USBH)
Function
OCR
27
19
11
0
0
0
3
BLF
26
18
10
0
0
0
2
SOC1
CLF
25
17
0
9
0
1
SOC0
HCR
24
16
0
8
0
0
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