UPD70F3768GF-GAT-AX Renesas Electronics America, UPD70F3768GF-GAT-AX Datasheet - Page 827
UPD70F3768GF-GAT-AX
Manufacturer Part Number
UPD70F3768GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3768GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3768GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
Note Set the SPTn bit to 1 only in master mode. However, to perform a master operation before detecting
Caution If the WRELn bit is set to 1 during the ninth clock and the wait state is canceled when the
Remarks 1. The SPTn bit is 0 if it is read immediately after data setting.
Cautions concerning set timing
For master reception:
For master transmission: A stop condition may not be generated normally during the ACK reception period. Set
• Cannot be set to 1 at the same time as the STTn bit.
• The SPTn bit can be set to 1 only when in master mode
• When the WTIMn bit has been set to 0, if the SPTn bit is set to 1 during the wait period that follows output of
• When the SPTn bit is set to 1, setting the SPTn bit to 1 again is disabled until the setting is cleared to 0.
Condition for clearing (SPTn bit = 0)
• Cleared by loss in arbitration
• Automatically cleared after stop condition is detected
• Cleared when the LRELn bit = 1 (communication
• When the IICEn bit = 0 (operation stop)
• After reset
SPTn
eight clocks, note that a stop condition will be generated during the high-level period of the ninth clock.
The WTIMn bit should be changed from 0 to 1 during the wait period following output of eight clocks, and the
SPTn bit should be set to 1 during the wait period that follows output of the ninth clock.
save)
0
1
the first stop condition after operation has been enabled when the IICRSVn bit is 0, the SPTn bit must
be set to 1 and a stop condition must be set. For details, see 19.15 Cautions.
TRCn bit is 1, the TRCn bit is cleared to 0 and the SDA0n line is set to high impedance.
2. n = 0 to 2
Stop condition is not generated.
Stop condition is generated (termination of master device’s transfer).
After the SDA0n line goes to low level, either set the SCL0n line to high level or wait until the SCL0n
pin goes to high level. Next, after the rated amount of time has elapsed, the SDA0n line is changed
from low level to high level and a stop condition is generated.
Cannot be set to 1 during transfer.
Can be set to 1 only when the ACKEn bit has been set to 0 and during the wait period
after the slave has been notified of final reception.
to 1 during the wait period that follows output of the ninth clock.
Stop condition trigger
Note
Condition for setting (SPTn bit = 1)
• Set by instruction
.
CHAPTER 19 I
Page 827 of 1408
2
C BUS
(4/4)
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