UPD70F3768GF-GAT-AX Renesas Electronics America, UPD70F3768GF-GAT-AX Datasheet - Page 1144
UPD70F3768GF-GAT-AX
Manufacturer Part Number
UPD70F3768GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3768GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Company:
Part Number:
UPD70F3768GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3-U, V850ES/JH3-U
21.7.4 Interruption from USB host controller
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
(1) USB status interrupt (INTUSBH0)
(2) Interrupt sources
system as one of the following three types of interrupts.
The USB host controller collects and sorts interrupts sent from the OHCI host controller and reports them to the
The details on each interrupt are as follows.
(a) Interrupt routing
Interrupts defined in the OpenHCI Specification are supported.
Use the HcInterruptEnable register to set interrupt sources reported to the system. Interrupts are reported via the
route specified with the IR bit.
The following lists the interrupt sources.
The OHCI host controller reports an occurrence of the INTA or SMMI interrupt to the system, according to the
setting of the IR bit of the HcControl register in OHCI operational registers. After reset, INTA is routed for
reporting the interrupt by the initial setting of the IR bit.
INTA and SMMI are used as the sources of interruption, except for Ownership Change.
To use the INTA and SMMI interrupt, the inta_en and int_smmi_en bits of the PCI interrupt control register of
PCI host bridge registers must be set (1).
INTUSBH0
INTUSBH1
INTUSBH2
Interrupt Report Signal to System
Table 21-6. Interruption from USB Host Controller
Table 21-7. Routing of Interrupts INTA and SMMI
IR Bit of HcControl Register
0
1
USBH status interrupt (INTA, SMMI or PME)
USBH PCI cycle error
USBH PME interrupt
Interrupt Report Signal Generated by OHCI Host Controller
CHAPTER 21 USB HOST CONTROLLER (USBH)
INTA (initial value)
SMMI
Interrupt Report Signal
Page 1144 of 1408
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