UPD70F3768GF-GAT-AX Renesas Electronics America, UPD70F3768GF-GAT-AX Datasheet - Page 360

• Manufacturer Part Number: UPD70F3768GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-U 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Ur

Specifications of UPD70F3768GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-U, V850ES/JH3-U
each time the valid edge of the external event count input is detected. Additionally, the set value of the TABnCCR0 register
is transferred to the CCR0 buffer register.
to 0000H, and a compare match interrupt request signal (INTTABnCC0) is generated.
value of TABnCCR0 register + 1) times.
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
TABnCTL0
TABnIOC0
TABnIOC2
TABnCTL1
When the TABnCE bit is set to 1, the value of the 16-bit counter is cleared from FFFFH to 0000H. The counter counts
When the count value of the 16-bit counter matches the value of the CCR0 buffer register, the 16-bit counter is cleared
The INTTABnCC0 signal is generated each time the valid edge of the external event count input has been detected (set
(a) TABn control register 0 (TABnCTL0)
(b) TABn control register 1 (TABnCTL1)
(c) TABn I/O control register 0 (TABnIOC0)
(d) TABn I/O control register 2 (TABnIOC2)
Remark
TABnOL3
TABnSYE
TABnCE
0/1
0
0
0
Figure 8-11. Register Setting for Operation in External Event Count Mode (1/2)
n = 0, 1
TABnOE3 TABnOL2 TABnOE2
TABnEST
0
0
0
0
TABnEEE
0
0
0
0
0
0
0
0
TABnEES1
TABnOL1
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
0/1
0
0
0
TABnEES0 TABnETS1 TABnETS0
TABnCKS2 TABnCKS1 TABnCKS0
TABnMD2 TABnMD1 TABnMD0
TABnOE1 TABnOL0 TABnOE0
0/1
0
0
0
0
0
0
0
0
0
0
1
0: Disable TOABn0 pin output
0: Disable TOABn1 pin output
Select valid edge
of external event
count input
0: Stop counting
1: Enable counting
0: Disable TOABn2 pin output
0: Disable TOABn3 pin output
0, 0, 1:
External event count mode
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