UPD70F3768GF-GAT-AX Renesas Electronics America, UPD70F3768GF-GAT-AX Datasheet - Page 687

• Manufacturer Part Number: UPD70F3768GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-U 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Ur

Specifications of UPD70F3768GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-U, V850ES/JH3-U
Remark
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
Other than above
ADA0FR3 to
ADA0FR0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Bits
Stabilization time:
Conversion time:
Wait time:
f
In the normal conversion mode, the conversion is started after the stabilization time elapses after the
ADA0M0.ADA0CE bit is set to 1, and A/D conversion is performed only during the conversion time (2.17 to 9.75
μ
(INTAD) is generated after the wait time elapses.
Because the conversion operation is stopped during the wait time, operating current can be reduced.
Cautions 1. Set as 2.17
XX
s). Operation is stopped after the conversion ends and the A/D conversion end interrupt request signal
:
Table 15-2. Conversion Time Selection in Normal Conversion Mode (ADA0HS1 Bit = 0)
26/f
52/f
78/f
100/f
100/f
100/fxx + 312/fxx + 314/f
100/fxx + 364/fxx + 366/f
100/f
100/f
100/f
100/f
100/f
100/f
100/f
100/f
100/f
Setting prohibited
+ Conversion Time + Wait Time
2. During A/D conversion, if the ADA0M0, ADA0M2, ADA0S, ADA0PFM, and ADA0PFT
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
+ 52/f
+ 104/f
+ 156/f
registers are written or a trigger is input, reconversion is carried out. However, if the
stabilization time end timing conflicts with writing to these registers, or if the stabilization
time end timing conflicts with the trigger input, a stabilization time of 64 clocks is
reinserted.
If a conflict occurs again with the reinserted stabilization time end timing, the stabilization
time is reinserted. Therefore do not set the trigger input interval and control register write
interval to 64 clocks or lower.
+ 208/f
+ 260/f
+ 416/f
+ 468/f
+ 520/f
+ 572/f
+ 624/f
+ 676/f
+ 728/f
+ 780/f
+ 832/f
Stabilization Time
XX
XX
XX
+ 54/f
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
+ 106/f
+ 158/f
Wait time inserted before the next conversion
A/D converter setup time (1
Actual A/D conversion time (2.17 to 9.75
Main clock frequency
+ 210/f
+ 262/f
+ 418/f
+ 470/f
+ 522/f
+ 574/f
+ 626/f
+ 678/f
+ 730/f
+ 782/f
+ 834/f
XX
μ
s ≤ conversion time ≤ 9.75
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
XX
Setting prohibited
5.46
8.17
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
μ
μ
s
s
A/D Conversion Time
48 MHz
μ
s or longer)
μ
s.
Setting prohibited
8.19
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
μ
s)
μ
s
32 MHz
CHAPTER 15 A/D CONVERTER
5.50
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
Setting prohibited
μ
s
24 MHz
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