UPD70F3768GF-GAT-AX Renesas Electronics America, UPD70F3768GF-GAT-AX Datasheet - Page 954

• Manufacturer Part Number: UPD70F3768GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-U 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Ur

Specifications of UPD70F3768GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
(21) UF0 INT clear 0 register (UF0IC0)
UF0IC0
Bit position
This register controls clearing the interrupt sources indicated by the UF0IS0 register.
This register is write-only, in 8-bit units. If this register is read, the value FFH is read.
FW can clear an interrupt source by writing 0 to the corresponding bit of this register. Even a bit that is
automatically cleared to 0 by hardware can be cleared by FW before it is cleared by hardware. Writing 0 to a bit of
this register automatically sets the bit to 1. Writing 1 is invalid.
7
6
4
3
2
1
0
RSTC
BUS
7
BUSRSTC
RSUSPDC
SHORTC
DMAEDC
SETRQC
CLRRQC
EPHALTC
Bit name
SPDC
RSU
6
This bit clears the Bus Reset interrupt.
This bit clears the Resume/Suspend interrupt.
This bit clears the Short interrupt.
This bit clears the DMA_END interrupt.
This bit clears the SET_RQ interrupt.
This bit clears the CLR_RQ interrupt.
This bit clears the EP_Halt interrupt.
5
1
0: Clear
0: Clear
0: Clear
0: Clear
0: Clear
0: Clear
0: Clear
SHORTC
4
DMA
EDC
3
CHAPTER 20 USB FUNCTION CONTROLLER (USBF)
RQC
SET
2
Function
RQC
CLR
1
HALTC
EP
0
0020003CH
Address
After reset
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FFH