AT91SAM7S32-AU-001 Atmel, AT91SAM7S32-AU-001 Datasheet - Page 295

• Manufacturer Part Number: AT91SAM7S32-AU-001
• Description: IC ARM7 MCU 32BIT 32K 48LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7S32-AU-001

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: I²C, SPI, SSC, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• For Use With: AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: AT91SAM7S32-AU001

Figure 29-6. Master Write with Multiple Data Byte
Figure 29-7. Master Write with One Byte Internal Address and Multiple Data Bytes
29.6.4
6175K–ATARM–30-Aug-10
TXCOMP
TXCOMP
TXRDY
TXRDY
TWD
TWD
Write THR (Data n)
Master Receiver Mode
S
Write THR (Data n)
S
DADR
DADR
The read sequence begins by setting the START bit. After the start condition has been sent, the
master sends a 7-bit slave address to notify the slave device. The bit following the slave address
indicates the transfer direction, 1 in this case (MREAD = 1 in TWI_MMR). During the acknowl-
edge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull
it down in order to generate the acknowledge. The master polls the data line during this clock
pulse and sets the NACK bit in the status register if the slave does not acknowledge the byte.
If an acknowledge is received, the master is then ready to receive data from the slave. After data
has been received, the master sends an acknowledge condition to notify the slave that the data
has been received except for the last data, after the stop condition. See
RXRDY bit is set in the status register, a character has been received in the receive-holding reg-
ister (TWI_RHR). The RXRDY bit is reset when reading the TWI_RHR.
When a single data byte read is performed, with or without internal address (IADR), the START
and STOP bits must be set at the same time. See
performed, with or without internal address (IADR), the STOP bit must be set after the next-to-
last data received. See
W
W
A
IADR(7:0)
A
Write THR (Data n+1)
DATA n
Figure
A
29-9. For Internal Address usage see
DATA n
Write THR (Data n+1)
A
AT91SAM7S Series Preliminary
A
Write THR (Data n+x)
DATA n+5
Last data sent
Figure
Write THR (Data n+x)
DATA n+5
Last data sent
29-8. When a multiple data byte read is
A
DATA n+x
A
(ACK received and TXRDY = 1)
Section
(ACK received and TXRDY = 1)
STOP sent automaticaly
DATA n+x
STOP sent automaticaly
Figure
29.6.5.
A
29-9. When the
A
P
P
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