AT91SAM7S32-AU-001 Atmel, AT91SAM7S32-AU-001 Datasheet - Page 577

IC ARM7 MCU 32BIT 32K 48LQFP

AT91SAM7S32-AU-001

Manufacturer Part Number
AT91SAM7S32-AU-001
Description
IC ARM7 MCU 32BIT 32K 48LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheets

Specifications of AT91SAM7S32-AU-001

Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
I²C, SPI, SSC, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
For Use With
AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
AT91SAM7S32-AU001

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91SAM7S32-AU-001
Manufacturer:
Atmel
Quantity:
10 000
Company:
Part Number:
AT91SAM7S32-AU-001
Quantity:
2 100
Table 37-23. SSC Timings (Continued)
Notes:
6175K–ATARM–30-Aug-10
Symbol
SSC
SSC
SSC
SSC
SSC
SSC
SSC
SSC
6
7
8
9
10
11
12
13
(1)
1. Timings SSC4 and SSC7 depend on the start condition. When STTDLY = 0 (Receive start delay) and START = 4, or 5 or 7
2. For output signals (TF, TD, RF), Min and Max access times are defined. The Min access time is the time between the TK (or
3. 3.3V domain: V
4. 1.8V domain: V
5. t
(Receive Start Selection), two Periods of the MCK must be added to timings.
RK) edge and the signal change. The Max access timing is the time between the TK edge and the signal stabilization.
37-16
Parameter
TF hold time after TK edge (TK input)
TK edge to TF/TD (TK input, TF input)
RF/RD setup time before RK edge (RK input)
RF/RD hold time after RK edge (RK input)
RK edge to RF (RK input)
RF/RD setup time before RK edge (RK output)
RF/RD hold time after RK edge (RK output)
RK edge to RF (RK output)
CPMCK
illustrates Min and Max accesses for SSC0. The same applies for SSC1, SSC4, and SSC7, SSC10 and SSC13.
: Master Clock period in ns
VDDIO
VDDIO
Figure 37-16. Min and Max access time of output signals
from 3.0V to 3.6V, maximum external capacitor = 40 pF.
from 1.65V to 1.95V, maximum external capacitor = 20 pF.
TK (CKI =0)
TK (CKI =1)
TF/TD
Receiver
Conditions
3.3V domain
1.8V domain
3.3V domain
1.8V domain
3.3V domain
1.8V domain
3.3V domain
1.8V domain
3.3V domain
1.8V domain
3.3V domain
1.8V domain
3.3V domain
1.8V domain
3.3V domain
1.8V domain
AT91SAM7S Series Preliminary
SSC
SSC
0max
0min
10 (+3*t
6 (+3*t
56.5 - t
t
26 - t
t
CPMCK
CPMCK
t
t
t
t
10.5
CPMCK
CPMCK
CPMCK
CPMCK
Min
CPMCK
6
0
0
CPMCK
0
0
(2)
CPMCK
(2)
(2)
CPMCK
(2)
- 5.5
- 10
)
(1)(2)
)
(1)(2)
29.5 (+3*t
56 (+3*t
Max
27
58
12
4
CPMCK
(2)
CPMCK
(2)
(2)
(2)
)
(1)(2)
)
(1)(2)
Units
Figure
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
577

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