AT91SAM7S32-AU-001 Atmel, AT91SAM7S32-AU-001 Datasheet - Page 685

• Manufacturer Part Number: AT91SAM7S32-AU-001
• Description: IC ARM7 MCU 32BIT 32K 48LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7S32-AU-001

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: I²C, SPI, SSC, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• For Use With: AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: AT91SAM7S32-AU001

40.14.8.8
40.14.8.9
40.14.8.10
40.14.8.11
40.14.9
40.14.9.1
6175K–ATARM–30-Aug-10
Synchronous Serial Controller (SSC)
SPI: Disable Issue
SPI: Software Reset and SPIEN Bit
SPI: CSAAT = 1 and Delay
SPI: Bad Serial Clock Generation on 2nd Chip Select
SSC: Periodic Transmission Limitations in Master Mode
Read first the received data, then perform the software reset.
The SPI Command “SPI Disable” is not possible during a transfer, it must be performed only
after TX_EMPTY rising else there is everlasting dummy transfers occur.
None.
The SPI Command “software reset” does not reset the SPIEN config bit. Therefore rewriting an
SPI enable command does not set TX_READY, TX_EMPTY flags.
Send SPI disable command after a software reset.
If CSAAT = 1 for current access and there is no more TX request for a time greater
than DLYBCT + DLYBCS, then if an access is requested on another slave, the NPCS bus
switches from one CS to the one requested without DLYBCS. External Slaves may reach a con-
tention on SPI_MISO line for a short period.
Assert the Last Transfer Command (NPCS de-activation) for the last character of each slave.
Bad Serial clock generation on the 2nd chip select when SCBR = 1, CPOL = 1 and NCPHA = 0.
This occurs using SPI with the following conditions:
Do not use a multiple Chip Select configuration where at least one SCRx register is configured
with SCBR = 1 and the others differ from 1 if NCPHA = 0 and CPOL = 1.
If all chip selects are configured with Baudrate = 1, the issue does not appear.
If the Least Significant Bit is sent first (MSBF = 0), the first TAG during the frame synchro is not
sent.
None.
• Master Mode
• CPOL = 1 and NCPHA = 0
• Multiple chip selects are used with one transfer with Baud rate (SCBR) equal to 1 (i.e., when
• Transmitting with the slowest chip select and then with the fastest one, then an additional
serial clock frequency equals the system clock frequency) and the other transfers set with
SCBR are not equal to 1
pulse is generated on output SPCK during the second transfer.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
AT91SAM7S Series Preliminary
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